Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-04-04
2003-03-25
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S203000, C365S189011
Reexamination Certificate
active
06538913
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for operating a ferroelectric memory configuration in the V
DD
/2 mode. The memory configuration has a large number of memory cells which each have at least one selection transistor, one storage capacitor with an upper and a lower electrode and one short-circuiting transistor whose source-drain junction is connected in parallel with the storage capacitor. After a read or write procedure in which the memory cells are driven via respectively associated word lines and via respectively associated bit lines, which are precharged in a precharge phase, the short-circuiting transistor is driven during a standby phase and in the process short-circuits the electrodes in the storage capacitor. The invention also relates to a ferroelectric memory configuration operated using this method.
A ferroelectric memory configuration which is operated using such a method is known from German Patent Document DE 19 832 994 (Siemens AG). The known method allows a ferroelectric memory which has a large number of memory cells to be operated in the V
DD
/2 mode without any refresh cycles.
In general, there is a risk with nonvolatile memories such as these, which are in the form of integrated circuits, that parasitic components will cause voltage differences at the electrodes of ferroelectric storage capacitors. Depending on the polarization of the dielectric of the storage capacitor and the polarity of the voltage differences, these voltage differences increase or decrease the polarization of the dielectric.
Thus, in the worst case, incorrect assessment of information when reading from the memory configuration can occur, and this corresponds to loss of data.
In the memory configuration described in the abovementioned document, the short-circuiting transistor, which is provided in parallel with the storage capacitor in each memory cell, is used to connect the memory nodes to the upper or top electrode plate of the storage capacitor, thus compensating for the junction leakage current of the memory node.
FIG. 1
is a schematic illustration showing a section through a known memory cell of a ferroelectric memory configuration that is equipped with such a short-circuiting transistor. It can clearly be seen, in this example of a memory cell, that the storage capacitor C is located under the bit line BL. The storage capacitor C has an upper plate or top electrode TE and a lower plate or bottom electrode BE. A ferroelectric dielectric D, for example composed of PZT (lead zirconium titanate), is located between the upper plate TE and the lower plate BE of the storage capacitor C. A number of n
+
-conductive zones are diffused in a semiconductor body which is, for example, a p-substrate. Word lines WL
0
, WL
1
, WL
2
, WL
3
, etc, which run at right angles to the plane of the paper in the section illustrated in
FIG. 1
, are located above the substrate and between the n
+
-conductive zones. The n
+
-conductive zones between adjacent word lines, for example, between WL
0
and WL
1
; WL
2
and WL
3
shown in
FIG. 1
, form common nodes CN.
A short-circuiting transistor SH which, for example, is a field-effect transistor of the depletion type, is located under the word line WL
2
between the memory node SN, which is connected to the lower capacitor electrode BE, and the adjacent n
+
-region, which is connected to the upper capacitor electrode BE. When an appropriate drive signal is present, the short-circuiting transistor SH connects the upper capacitor electrode TE to the lower capacitor electrode BE, that is to say it short-circuits the two electrodes. Considered over the entire memory configuration, a short-circuit between all of the storage capacitors C can compensate for the entire junction leakage current I
jct
.
FIG. 2
uses a signal/time diagram to show the method proposed in the above document for V
DD
/2 operation of the ferroelectric memory configuration with compensation for the junction leakage current I
jct
of each memory node SN.
When the memory configuration is switched on, all of the word lines WL are at zero volts. In an initial phase STB, an electrode which is common to all of the storage capacitors C and that can be connected or is connected to TE of the capacitor C is raised to the voltage V
DD
/2, for example to 0.9 volts. Since the threshold voltage of the short-circuiting transistors SH is now chosen to be correspondingly strongly negative, these short-circuiting transistors SH still conduct even when the electrode which is common to all of the storage capacitors C has been charged to V
DD
/2. Thus, during the initial phase STB, both electrodes of all of the ferroelectric storage capacitors C are short-circuited. In consequence, the compensation for the junction leakage currents I
jct
takes place. In this case, in a conventional 4-memory configuration, a standby current flows, defined by:
I
stb1
=2
22
·I
jct
+2
21
·I
jct
(1)
In equation (1), the first term is governed by the memory nodes SN, and the second term by the common nodes CN.
Assuming typical values for 256-MDRAM technology (I
jct
=20 fA), then the standby current is:
I
stb1
=125
nA.
This phase STB, in which the storage capacitor C is short-circuited, is followed by a precharge step PRE in that, first, all of the bit lines BL to be addressed are set to zero volts and the selection transistors are switched off. The precharge step PRE is followed by access to selected memory cells, for example to the memory node SN illustrated in FIG.
1
. Since the corresponding word line WL, that is to say the word line WL
1
in the example in
FIG. 1
, is charged from zero volts to the full supply voltage V
DD
or more, the desired ferroelectric storage capacitors C are connected to the corresponding bit lines. Since the addressed bit lines BL are precharged to 0 V by the precharge step PRE, a displacement current can flow through the ferroelectric capacitor C, with charge equalization taking place between the selected ferroelectric storage capacitors and the associated bit lines. This step is symbolized in
FIG. 2
by the step READ. However, before this takes place, the gates of the short-circuiting transistors which short-circuit the selected ferroelectric storage capacitors C must be switched off. This is done by applying a negative potential to the word line corresponding to the short-circuiting transistor SH, that is to say, in the example in
FIG. 1
, to the word line WL
2
. This negative potential switches off only the desired field-effect transistors of the depletion type. Field-effect transistors of the enhancement type, which are likewise connected to the word line WL
2
, have already been switched off by the standby potential in the precharge step, and the negative potential only increases the high impedance further.
After assessment of the read signal READ and its amplification in the SENSE step, the selected word line, that is to say, for example, WL
1
, is discharged to zero volts once again, thus disconnecting the selected memory cells from the bit lines BL once again. In order to reproduce the short-circuit of the electrodes of the ferroelectric storage capacitor C, the short-circuiting transistor SH is switched on by discharging the word line WL
2
corresponding to the short-circuiting transistor SH to zero volts. Finally, the word line WL
1
is then discharged to zero volts in order to disconnect the selected memory cells from the bit lines BL once again.
FIG. 1
shows that, apart from the leakage current I
jct
, a subthreshold leakage current I
sth
also flows in the precharge phase PRE, but this is less than the junction leakage current I
jct
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for operating a ferroelectric memory configuration and a ferroelectric memory configuration which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention
Hönigschmid Heinz
Röhr Thomas
Greenberg Laurence A.
Lam David
Lerner Herbert L.
Stemer Werner H.
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