Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-02-14
2003-03-04
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S018000
Reexamination Certificate
active
06528335
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to evaluating the buried oxide of silicon-on-insulator wafers and more particularly, carrying out current-voltage measurements and analyzing the current-voltage behavior in terms of short circuit defect densities, low voltage breakdown defects, and excess current leakage defects.
BACKGROUND OF THE INVENTION
Silicon-on-insulator (SOI) starting substrate material can be used as an alternative to standard silicon (Si) wafers (“bulk silicon”) to produce integrated circuits. Quality control of starting SOI wafers is necessary because such wafers are produced in “batch” processes which can have variability in defect densities, interface perfection, and contamination. Such quality control includes determining the electrical quality of the buried oxide (BOX) which serves to isolate the superficial Si layer where the devices and circuits are fabricated from the substrate, resulting in advantages of speed, lower power needed to run the circuits, and better immunity from “soft error events” caused by penetration of damaging incident particles (such as alpha rays).
Since silicon dioxide (SiO
2
) has a dielectric breakdown strength of over 10 Megavolts per centimeter and passes only extremely small electric currents below this breakdown voltage, and since the BOX of SOI substrates is mostly SiO
2
, it might be expected that the electrical properties of the BOX would exhibit high dielectric strength and low leakage currents also. This is generally true for the “Bonded” form of SOI substrates in which the substrate is fabricated by bonding two silicon wafers together with a layer of SiO
2
in-between and thinning one of the wafers of this connected pair to the desired thickness. However, the SIMOX (“separation by implantation of oxygen”) form of SOI wafer, in which the substrate is created by implantation of a high or low dose of oxygen and subsequently annealed at very high temperatures for time periods sufficient for the implanted oxygen alone or the implanted and diffused oxygen to form an SiO
2
layer beneath the wafer surface, contains several types of defects (asperities) which affect the oxide electrically. One form of defect commonly found in SIMOX wafers consists of crystalline silicon precipitates (Si islands) located inside the BOX. Such defects are easily observed by transmission electron microscopy (TEM). Crystalline silicon precipitates inside the BOX have electrical consequences because crystalline silicon precipitates alter the electric field inside the BOX when a voltage is applied across it, increasing the leakage current and lowering the breakdown voltage. Such defects have been described, for example, by K. Kawamura et al, IEEE Internat. SOI Conference, 1997, page 122. When the BOX electrical breakdown occurs in the vicinity of one of these crystalline silicon precipitates, the temperature increases to the degree that the precipitate and its surrounding material is vaporized and the breakdown region consequently heals itself. An increase of voltage then causes a repeat of this self-healing premature breakdown at another crystalline silicon precipitate, and so on until all of the crystalline silicon precipitate regions have broken down or the final dielectric breakdown of the precipitate-free region takes place.
The BOX also contains other asperities such as amorphous silicon “clusters” dispersed throughout the BOX which are only a few tens of nanometers in size and not detected by TEM. Such defects have been described, for example, by A. G. Revesz et al, IEEE Internat. SOI Conference, 1993, page 24. They can cause excess leakage currents through the BOX, exacerbated by the concentration of the electric field by crystalline Si islands. In addition, SIMOX buried oxides may contain “pinholes” or “pipes” where the oxide may be bridged by Si regions (see, for example, Mrstik et al, Appl. Phys. Lett. Volume 67, page 3283, 1995; and K. Kawamura et al, IEEE Internat. SOI Conf., 1995, page 156).
All of these defects can cause lower yield and reduced reliability in processed circuits. The Si pipes result in short circuits between the substrate and the Si layer. The amorphous clusters and crystalline Si islands result in excess leakage currents which can cause charge trapping and device threshold voltage shifts. The crystalline Si islands result in lower breakdown voltages and can result in damage to the Si layer and BOX during high voltage processing steps such as plasma etching, plasma deposition, and the like. For these reasons, it is desirable for quality control purposes to detect the extent of these defects in the starting material before the expensive and time-consuming circuit processing has begun.
SUMMARY OF THE INVENTION
The short circuit defect density, the leakage current, and the premature, self-healing breakdowns (known as mini-breakdowns) can all be determined by the practice of the invention, resulting in quality control of the starting material which impacts yield, reliability, and performance. The electrical test structure is made by depositing a metal such as aluminum on the back of the substrate, depositing gold “dots” on the superficial semiconductor such as a Si containing layer surface above the buried oxide, contacting the Si layer with an etchant which removes the Si layer in-between the Au dots. The sample is then placed onto a measurement stage which electrically contacts the Al layer on the back side of the substrate or wafer and one of the Au dots above the superficial Si layer, performing a current-voltage measurement: a) with a fixed low voltage less than the first mini-breakdown voltage (fixed low voltages of 5 to 20 volts are typical), “stepping” at a high rate (one dot per second is typical) to contact as many of the Au dots as desired while recording the current, b) with a higher fixed voltage less than the first mini-breakdown (fixed voltages of 25 to 50 volts are typical) and stepping at a lower rate (one dot per minute is typical) for as many Au dots as desired while recording the current, c) applying a ramp voltage from a low voltage up to the expected dielectric breakdown voltage (typically applying a ramp voltage from 20 volts to 100 volts) while monitoring the current using a fast response time measurement circuit. The measurement in (a) determines the short circuit defect density; the measurement in (b) determines the leakage current; the measurement in (c) determines the mini-breakdown defect density and the voltages at which they occur. A second technique for detecting the occurrence of a mini-breakdown event is to monitor the light output from the Au dot being measured, since each mini-breakdown is accompanied by a strong light flash.
REFERENCES:
patent: 5786231 (1998-07-01), Warren et al.
patent: 6074886 (2000-06-01), Henaux
Mrstik et al., “Improvement in electrical properties of buried SiO2 layers by high-temperature oxidation”, Nov. 1995, Appl. Phys. Lett. 67 (22), pp. 3283-3285.*
K. Kawamura et al., “Experimental Verification of Buried-Oxide with Over-8MV/cm Breakdown Fields in Low-Dose SIMOX Wafers”, Oct. 1997, Proceedings 1997 IEEE International SOI Conference, pp. 122-123.*
K. Kawamura et al., “Improvement of Buried Oxide Quality in Low-Dose SIMOX Wafers by High-Temperature Oxidation”, Oct. 1995, Proceedings 1995 IEEE International SOI Conference, pp. 156-157.*
Revesz et al., “Photo-Injection Studies of Buried Oxide Layers in SIMOX and BESOI Structures”, 1993, Proceedings 1993 International SOI Confernce, pp. 24-25.*
S. Nakashima et al., Electrical Characteristics of the Interface between the Top Si and Buried Oxide in ITOX-SIMOX Wafers, Oct. 1998, Proceedings 1998 IEEE International SOI Conference, pp. 19-20.*
S. Henaux et al., “Gate Oxide Integrity Testing on SOI Wafers without Test Structure Fabrication”, Oct. 1998, Proceedings 1998 IEEE International SOI Conference, pp. 87-88.*
Y. Gu et al., “SOI Material Characterization Using Optical Second Harmonic Generation”, Oct. 1995, Proceedings 1995 IEEE International SOI Conference, pp. 94-95.*
G. Brown et al., “Moat Edge Oriented Defe
Almonte Marlene Isabel
Hovel Harold John
Kleinhenz Richard Leo
Pert Evan
Sherry Michael
Trepp Robert M.
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