Semiconductor memory array of floating gate memory cells...

Details Semiconductor memory array of floating gate memory cells... Semiconductor memory array of floating gate memory cells...

2001-08-16

2003-05-13

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000, C257S319000, C257S321000

Reexamination Certificate

active

06563167

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells of the split gate type. The present invention also relates to a semiconductor memory array of floating gate memory cells of the foregoing type.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
In the split-gate architecture, the memory cells can be formed in mirrored pairs arranged end to end along columns, with the columns separated by columns of isolation areas.
FIG. 1A
illustrates a partially formed pair of memory cells, with floating gates
1
disposed over a substrate
2
. A source region
3
is formed in the substrate
2
, and is electrically connected to a source line
4
. Insulating materials
5
insulate floating gate
1
, substrate
2
, source regions
3
and source line
4
from each other. Control gates
6
are formed adjacent and over, but insulated from, the floating gates
1
. Control gates
6
extend over drain regions
7
formed in the substrate.
FIG. 1B
is an orthogonal view that illustrates the isolation regions
8
formed of insulation material that separates the columns of memory cells. A sharp edge
9
is formed on the floating gate to enhance Fowler-Nordheim tunneling between the floating gate
1
and control gate
6
.
One problem with this configuration is that sharp edge
9
is typically formed using an anisotropic etch, which can result in the flattening of edge
9
if the block or spacer edge used to screen the etch process is not perfectly vertical. Additionally, as the design rules shrink, better Fowler-Nordheim tunneling between the floating gate and control gate for many application will be needed, despite the use of a sharp edge on the floating gate.
There is a need for a memory cell fabrication process that ensures the sharpness of the floating gate sharp edge, and enhances the Fowler-Nordheim tunneling between the floating and control gates.
SUMMARY OF THE INVENTION
The present invention addresses the aforementioned needs by providing a self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, where sharp edges on the floating gates can be reliably formed. The floating gate memory cells, and particularly the sharp edges on the floating gates, are easier to manufacture. The present invention lowers the coupling ratio between the control gate and the floating gate for better erase of the memory cell. Further, enhanced erase speeds are available given the limited wordline coverage of the floating gate sharp edges.
The present invention is a self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, where each memory cell has a floating gate, a first region, a second region with a channel region therebetween, and a control gate. The method comprises the steps of:
a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, each of the active regions comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
b) etching a top portion of the first layer of conductive material to form a pair of raised opposing sharp edges in the first layer of conductive material in each of the active regions that have a length extending in the first direction;
c) etching portions of the first layer of conductive material to form a plurality of discrete floating gates in each of the active regions, wherein each floating gate includes a portion of the raised opposing pair of sharp edges;
d) forming a plurality of spaced apart blocks of electrically conductive material in each of the active regions, wherein each of the blocks partially overlaps with and is isolated from one of the floating gates;
e) forming a plurality of first regions in the substrate, wherein in each of the active regions, each of the floating gates partially overlaps with and is isolated from one of the first regions; and
f) forming a plurality of second regions in the substrate, wherein in each of the active regions each of the second regions is spaced apart from the first regions.
In another aspect of the present invention, an electrically programmable and erasable memory device includes a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween, a first insulation layer disposed over said substrate, an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of the channel region and over a portion of the first region, wherein the floating gate includes a pair of opposing raised sharp edges, a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and an electrically conductive control gate having a first portion disposed adjacent to and insulated from the floating gate and a second portion extending over a portion of the second insulation layer and over a portion of the floating gate including a portion of both of the raised sharp edges.
In yet another aspect of the present invention, an array of electrically programmable and erasable memory devices includes a substrate of semiconductor material of a first conductivity type, and spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions. Each of the active regions includes a plurality of memory cells extending in the first direction. Each of the memory cells includes first and second spaced-apart regions formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween, a first insulation layer disposed over said substrate including over said channel region, an electrically conductive floating gate disposed over the first insulation layer and extending over a portion of the channel region and over a portion of the first region, wherein the floating gate includes a pair of opposing raised sharp edges, a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and an electrically conductive control gate having a first portion disposed adjacent to and insulated from the floating gate and a second portion extending over a portion of the second insulation layer and over a portion of the floating gate including a portion of the pair of raised sharp edges.
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