Semiconductor device

Details Semiconductor device Semiconductor device

2002-01-28

2003-05-27

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06570236

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns a semiconductor device, and in particular, concerns a mask ROM, into which information is written during the manufacturing process.
2. Prior Arts
With prior-art mask ROM's, the contact method, with which of the respective wiring layers of the source line, word line, and bit line that comprise a memory cell, the wiring layer of the bit line is formed last and the writing of information is performed by making a contact hole exist or non-existent between the bit line and each cell, has been known as a means of shortening the TAT (Turn Around Time), which is the period between the acquisition of ROM data from a customer to the shipment of a product or is the period, in the process of forming elements and wirings on a semiconductor substrate (shall be referred to hereinafter as “semiconductor treatment process”), from the process of writing the ROM data to the completion of the abovementioned semiconductor treatment process. This prior art shall now be described more specifically by the use of drawings.
FIG. 1A
is a circuit diagram of a prior-art semiconductor device,
FIG. 11B
is a perspective view, which shows the planar layout of the same semiconductor device,
FIG. 12A
is a sectional view along line III—III of
FIG. 11B
, and
FIG. 12B
is a sectional view along line IV—IV of FIG.
11
B. In
FIGS. 11A
,
11
B,
12
A, and
12
B,
1
is a Si substrate,
2
is a field oxide film of SiO
2
, which becomes an element separation region formed on substrate
1
,
3
is a word line,
22
is a drain diffusion layer,
23
is a ground-potential source diffusion layer,
24
is a bit line of a fourth wiring layer,
25
is a wiring that is electrically connected to a word line of a fifth wiring layer and lowers the resistance of the word line (backing wiring of the word line),
10
is a first wiring layer,
11
is a second wiring layer,
12
is a third wiring layer,
15
is a contact hole, which connects drain diffusion layer
22
and first wiring layer
10
,
16
is a contact hole, which connects first wiring layer
10
and second wiring layer
11
,
17
is a contact hole, which connects second wiring layer
11
and third wiring layer
12
,
18
is a contact hole, which connects third wiring layer
12
and bit line
24
of the fourth wiring layer, and
20
is an interlayer insulating film. Contact hole
18
is a contact hole for information writing, and information is written by making contact hole
18
exist or non-existent.
Since the fifth wiring layer, which is the uppermost layer, is provided with a backing wiring
25
for the word line, information-writing contact hole
18
is formed between fourth wiring layer
24
and third wiring layer
12
. When an information-writing contact hole
18
exists, bit line
24
is connected to drain diffusion layer
22
, via contact hole
18
, third wiring layer
12
, contact hole
17
, second wiring layer
11
, contact hole
16
, first wiring layer
10
, and contact hole
15
, and when contact hole
18
does not exist, bit line
24
is not connected to drain diffusion layer
22
.
The information reading operation is carried out as follows. First, prior to reading, bit line
24
is precharged to the “H” level (power supply voltage level) by a precharging circuit (not shown). The word line
3
that corresponds to the read address of the information is then set to the “H” level (power supply voltage level). At this point, if bit line
24
is connected to the drain diffusion layer
22
of the memory cell transistor, with which the gate electrode is coupled to the word line
3
of the “H” level, the transistor enters the ON state and bit line
24
is discharged to the “L” level (ground level). On the other hand, if there is no contact hole
18
and drain diffusion layer
22
and bit line
24
are not connected, since the transistor will then be cut off electrically from bit line
24
, bit line
24
will be kept as it is at the “H” level. Information of 0 or 1 is then output upon judging whether the level of bit line
24
is “L” or “H” by means of a sense amp circuit (not shown) connected to bit line
24
.
With the employment of multiple layer wiring in semiconductor devices in recent years, it is being demanded that information be written by making a contact hole exist or non-existent at an upper layer in a process close to the end of the abovementioned semiconductor treatment process in order to shorten the TAT.
With the above-described prior-art semiconductor device, the capacitance, which a bit line
24
is provided with, is comprised of the capacitance between this bit line
24
and an adjacent bit line
24
, the capacitance between the contact holes
15
,
16
,
17
, and
18
and wiring layers
10
,
11
, and
12
, which connect bit line
24
to drain diffusion layer
22
, and the adjacent contact holes
15
,
16
,
17
, and
18
and wiring layers
10
,
11
, and
12
, and the capacitance of drain diffusion layer
22
. When an information-writing contact hole is thus located at an upper layer of a multilayer wiring structure, since the number of contact holes and wiring layers for connecting bit line
24
and drain diffusion layer
22
increases, the capacitance at the contact hole and wiring layer parts increases, causing the precharge time and discharge time of bit line
24
to increase and the power consumed by bit line
24
to increase.
Also, in order to make the area of the memory cell small, the backing wiring
25
of the word line is formed from the fifth layer, which is the uppermost layer, and bit line
24
is formed from the fourth wiring layer. Since contact hole
18
for writing information therefore could not be made a contact hole immediately below the uppermost wiring layer, the TAT could not be made short.
SUMMARY OF THE INVENTION
An object of this invention is to provide a semiconductor device, which, despite being of a multilayer wiring structure, is short in the TAT and with which the increase of the capacitance of the bit line is restrained to shorten the precharge time and discharge time of the bit line and enable lowering of the consumption power.
A semiconductor device of this invention is comprised of a drain diffusion layer, which is formed on a semiconductor substrate and is in common to first and second transistors that make up a memory cell pair, a source diffusion layer for the first transistor and a source diffusion layer for the second transistor, which are formed on the semiconductor substrate in a manner whereby they are spaced from the drain diffusion layer by predetermined intervals so as to sandwich the drain diffusion layer, a first word line, which is coupled to a gate electrode of the first transistor, a second word line, which is coupled to a gate electrode of the second transistor, a bit line, which is arranged from a first wiring layer above the semiconductor substrate and is connected to the drain diffusion layer, and a source line, which is arranged from a second wiring layer above the first wiring layer above the semiconductor substrate, and with this semiconductor device, the writing of information is performed by making a connection exist or non-existent between the respective source diffusion layers of the first and second transistors and the source line.
With the arrangement of this invention, the source line is arranged as an upper wiring layer, the bit line is arranged as a lower wiring layer, and the writing of information is performed, regardless of the connection relationship of the bit line, by connection
on-connection of the source diffusion layer and the source line. This connection
on-connection part can thus be made a contact hole at the uppermost wiring layer or below to shorten the TAT, and since the capacitance of the bit line is not increased, high-speed operation with a short bit line precharge time and discharge time can be realized and the consumption power can be lessened.
In this case, contact parts, which are arranged from a wiring layer that is one layer below the second wiring layer that comprise

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