Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-18
2003-07-08
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06590254
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device with a memory cell region and a peripheral circuit region and a method of manufacturing such a device, and more particularly to a nonvolatile semiconductor memory device designed to prevent variations in the characteristics of transistors in the peripheral circuit region and a method of manufacturing such a device.
2. Description of the Related Art
FIG. 1A
is a plan view showing a conventional nonvolatile semiconductor memory device, and
FIG. 1B
is a cross-sectional view taken along a line L—L in FIG.
1
A. Furthermore, FIG.
2
A and FIG.
2
B through to FIG.
7
A and
FIG. 7B
show the sequence of steps for a method of manufacturing a conventional nonvolatile semiconductor memory device.
As shown in FIG.
1
A and
FIG. 1B
, an element isolating insulation film
114
is formed on the surface of a silicon substrate
110
, and a peripheral circuit region S
4
and a memory cell region S
5
are isolated each other by the element isolating insulation film
114
. Within the peripheral circuit region S
4
, the element isolating insulation film
114
is also formed around a transistor formation region, and a gate insulation film
126
is formed on the silicon substrate
110
in this region surrounded by the element isolating insulation film
114
. In addition, a gate electrode
134
is formed on the gate insulation film
126
, and one end of this gate electrode
134
is formed so as to extend out over the element isolating insulation film
114
. Within the memory cell region S
5
, a plurality of strip-like regions are partitioned off by the element isolating insulation film
114
, and a gate insulation film
112
is formed on the silicon substrate
110
in these strip-like regions. A control gate
130
is then formed from a plurality of lines which extend in a direction perpendicular to the lengthwise direction of these strip-like gate insulation films
112
, and the tips of every second control gate line are then connected to form a comb shaped pattern. The base layer of the control gate
130
comprises a floating gate
120
a
formed on the gate insulation film
112
, and an ONO film (a three layer construction comprising a silicon oxide film, a silicon nitride film, and another silicon oxide film)
124
formed thereon. A diffusion layer (not shown in the drawings) is formed on the surface of the silicon substrate
110
below the gate insulation film
112
in the region where the floating gate
120
a
is formed, and this diffusion layer is shared between adjacent memory elements. Furthermore, a dummy pattern
136
is formed between the peripheral circuit region S
4
and the memory cell region S
5
, and during operation of the nonvolatile semiconductor memory device this dummy pattern
136
is connected to GND.
As follows is a description of a method of manufacturing a conventional nonvolatile semiconductor memory device. As shown in FIG.
2
A and
FIG. 2B
, an element isolating region
114
is formed on the surface of a p-type silicon substrate
110
, surrounding both the transistor formation region of the peripheral circuit region S
4
and the memory element formation region of a memory circuit region. A gate insulation film
112
is then formed on the silicon substrate
110
in the aforementioned transistor formation region and memory element formation region, and a first poly-silicon film is subsequently formed on the entire surface. A resist film is then formed with a resist pattern
118
which is opened with the exception of the regions above the gate insulation films
112
of the peripheral circuit region S
4
and the memory cell region S
5
. This resist pattern
118
is then used as a mask for patterning the first poly-silicon film of the memory cell region S
5
, and forming a base layer
120
of a floating gate electrode of the memory cell region S
5
. At this point, the poly-silicon film
116
of the peripheral circuit region S
4
is not removed, as it prevents the ion injection used for forming a channel stopper in the subsequent process. Channel stopper ions are then injected using the resist pattern
118
, the poly-silicon film
116
and the base layer
120
as a mask. In this process, because the silicon substrate
110
is a p-type substrate, boron (B) ions which are capable of forming a p-type region of the same type of conductivity as the silicon substrate
110
are injected. This ion injection process is conducted for the following reasons. Namely, as the width of the element isolating region
114
for isolating memory elements decreases with increasing miniaturization of the memory cells, the thickness of the element isolating region decreases in comparison with other element isolating regions of a sufficiently large size. This decrease in thickness produces adverse effects such as a deterioration in the isolating capabilities, allowing current to flow between adjacent channels. In order to prevent such effects, a p-type region known as a channel stopper, with a higher concentration than the silicon substrate
110
, is formed in the internal section and the lower section of the element isolating region
114
.
Subsequently, following removal of the resist pattern
118
, a resist pattern
122
is formed which covers the floating gate base layer
120
of the memory cell region S
5
, and the poly-silicon film
116
in the peripheral circuit region S
4
is removed by dry etching, as shown in FIG.
3
A and FIG.
3
B. In order to ensure that the resist pattern
122
formed in the memory cell region S
5
results in the removal of all of the poly-silicon film
116
of the peripheral circuit region S
4
, the resist pattern
122
should be formed so that the edge on the side of the peripheral circuit region S
4
does not overlap with the edge of the poly-silicon film
116
on the side of the memory cell region S
5
. When the poly-silicon film
116
is removed, a portion of the gate insulation film
112
underneath the poly-silicon film
116
is also removed. The gate insulation film
112
of the peripheral circuit region S
4
is then removed completely using wet etching.
Subsequently, following removal of the resist pattern
122
, an ONO film
124
is formed on the entire surface, as shown in FIG.
4
. This ONO film
124
is an insulation film preventing the escape of electric charge retained by the floating gate electrode of the memory elements.
The ONO film
124
is optimized for film formation on top of the floating gate electrode, but is unsuitable as a gate insulation film for the transistors of the peripheral circuit region S
4
. Consequently, a resist pattern
125
is formed which is opened above the peripheral circuit region S
4
, and this resist pattern
125
is then used as a mask to remove the ONO film
124
in the peripheral circuit region S
4
, as shown in FIG.
5
A and FIG.
5
B. The removal of the ONO film
124
can utilize either dry etching removal methods or wet etching removal methods. Gate oxidation is then carried out, forming a gate insulation film
126
in the peripheral circuit region S
4
, and the resist pattern
125
is then removed.
Subsequently, a second poly-silicon film is formed on the entire surface, and a further resist film then formed thereon, forming a resist pattern
128
which covers the peripheral circuit region S
4
but is opened above the memory cell region S
5
with the exception of the control gate electrode formation region. The control gate
130
of the memory cell region S
5
then undergoes patterning, as shown in FIG.
6
A and FIG.
6
B. The control gate
130
is formed on the floating gate
120
a
with the ONO film
124
disposed therebetween. A region
138
where the second poly-silicon film has been removed by patterning is carved into the element isolating region
114
underneath. The resist pattern
128
is then removed.
Finally, as shown in FIG.
7
A and
FIG. 7B
, a resist pattern
132
is formed which covers the memory cell region S
5
but is opened above the peripheral circuit region S
4
wit
Choate Hall & Stewart
Fahmy Wael
NEC Electronics Corporation
Weiss Howard
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