Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-07-15
2003-01-14
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S100000, C712S225000
Reexamination Certificate
active
06507920
ABSTRACT:
This invention relates generally to automatic test equipment, and more particularly to extending synchronous busses in automatic test systems that test synchronous bus devices.
BACKGROUND OF THE INVENTION
Modern computer systems employ high-speed synchronous busses for communicating data. Synchronous busses coordinate operations on a bus by providing a common clock to all bus devices. Asynchronous busses do not use a common clock to coordinate activities. Examples of synchronous busses include PCI, AGP, and Cardbus.
Manufacturers of electronic circuit boards employ automatic test equipment (“ATE” or “testers”) to ensure that their products meet requirements for performance and functionality. In one testing configuration, a unit under test (“UUT”) is attached to a tester via one or more interface connectors, and the tester exercises the UUT by reproducing the UUT's native environment. Where the UUT is itself a synchronous bus card, a tester might reproduce the bus environment by including a complete synchronous bus to which the UUT connects.
Certain characteristics of synchronous busses make ATE testing of synchronous bus cards problematic. A primary limitation of synchronous busses is that in order to operate at high speed they must generally be kept short. Synchronous busses that operate at 33 MHz and above are seldom more than one foot long. The need to keep synchronous busses short forces the entire bus with all of its accompanying hardware and cooling into a location near the tester interface. The area around the tester interface tends to be crowded already, however. In addition to being the focal point of most of the tester's resources, the tester interface typically also includes test adapters, auxiliary equipment, and handlers for loading and unloading UUTs. Therefore, the need to keep synchronous busses short conflicts with the lack of available space near the tester interface.
Synchronous busses also tend to suffer from poor fault isolation. Defects on one card can appear as failures on other cards, and can cause an entire bus to malfunction. A benchmark of successful ATE is the ability to isolate faults. The lack of fault isolation common to most synchronous busses directly conflicts with the need for high fault isolation in ATE.
Some synchronous busses support changing bus cards with power applied, and can identify a new card “live” without requiring an explicit reset (a feature known as “hotswapping”). Many busses are not set up to allow cards to be quickly changed, however. These busses must be powered down before a card can be inserted or removed, and a time-consuming reset must be performed before normal operation can resume. ATE systems typically test a large volume of cards in assembly-line fashion. For busses that do not support hot-swapping, the time-consuming procedure for swapping cards conflicts with the ATE requirement of high throughput.
FIG. 1
illustrates a synchronous bus of the type that is commonly used in modern computer systems, and illustrates the need for synchronous busses to be kept short. Clock driver
112
buffers a master clock signal
114
and provides an individual version of the master clock to each clock receiver
120
on each device
122
,
124
, and
126
plugged into the bus
110
. The clock driver
112
distributes the master clock signal
114
to all slots on the bus with nearly zero timing skew: that is, nearly zero phase difference appears between the clock signals on the different slots of the bus.
As shown in
FIG. 1
, each device
122
,
124
, and
126
on the bus
110
includes a data transmitter
116
, a data receiver
118
, and a clock receiver
120
. The bus
110
is arranged in a multi-drop, multi-master configuration, in which any device can transmit or receive data from any other device on the bus. For example, device
122
can transmit data signals using its transmitter
116
to device
126
, and device
126
can then receive the data signals using its receiver
120
.
FIG. 1
identifies “T
prop
” as the time required for data signals to travel down the bus and settle. T
prop
is a finite delay related to a number of factors, including the bus' physical length, its impedance, the impedance of devices on the bus, inductive and capacitive loading, and bus terminations. If the period of the master clock
114
is much longer than T
prop
, data signals from device
122
have adequate time to travel down the bus and settle at device
126
before the next clock edge. If T
prop
approaches or exceeds the clock period, however, device
126
receives its clock edge before the data signals settle, and invalid clocking can occur. For proper operation, T
prop
must always be less than the clock period. The practical result of the requirement that T
prop
be less than the clock period is that very fast synchronous busses tend also to be very short.
Various techniques have been used to extend the length of synchronous busses, with partial success. These techniques include changing bus loading, slowing down the bus, bridging, and remote bus control.
Changing Bus Loading
Delay time T
prop
depends not only upon a bus' physical length, but also upon its electrical loading. By reducing bus loading, it may be possible to physically extend a bus and still keep T
prop
shorter than the clock period.
As a practical matter, reducing bus loading produces only small gains. Most bus implementations aggressively control bus loading, and leave little margin for improvement. Under the best conditions, reducing bus loading allows synchronous busses to be extended only a few inches. In an ATE environment, this improvement is too small to be useful.
Slowing Down the Bus
As the clock period of a bus limits its maximum length, one can theoretically lengthen a bus by slowing its clock period. The longer the clock period, the further data can travel before false clocking occurs.
Slowing the clock period seems to be a simple and attractive way of extending a bus, but this technique has several drawbacks. First, not all busses allow their clock periods to be changed. Second, running a bus at reduced speed slows operations on the bus, and can reduce the throughput of an entire system. Third, extending a bus adds loading to the bus and can cause ringing in the clock signal, which ringing itself can cause false clocking. Reducing the clock period does not reduce the ringing. In some circumstances, however, slowing the edges of the clock does reduce ringing. Slowing clock edges is difficult to achieve in practice, however. Last, testing UUTs at reduced speed can fail to reveal certain types of defects. Many faults manifest themselves only when a UUT is operated at its rated speed. Slowing the clock sacrifices fault detection, and thus conflicts with a primary purpose of ATE.
Bridging
FIG. 2
illustrates bus bridging, a commercially available technique for extending synchronous busses. One product that appears to provide a form of bus bridging is the model
2130
available from SBS Technologies, Inc., St. Paul, Minn. As shown in
FIG. 2
, a bridge device
218
straddles an original synchronous bus
210
and an extended synchronous bus
212
. The bridge device
218
copies signals between busses
210
and
212
and allows a remote device
216
to communicate back and forth with a local device
214
. Bridging effectively connects busses in series while electrically isolating the busses from each other. Multiple bridge devices can be cascaded to extend a bus even further.
Each bus segment that forms part of a bridged configuration must conform to the specification of the bus for maximum length. Thus, bridging allows busses to be cascaded, but does not extend the length of any individual bus segment. Therefore, bridging does not address the need to keep the area around the UUT clear.
Remote Bus Control
Remote bus control has been used to extend synchronous busses by long distances. One product that appears to provide a form of remote bus control is the model TA300 from Catalyst Enterprises, Inc., San Jose, Calif. Remote bus control operates by t
Beausoleil Robert
Rubenstein Bruce D.
Teradyne, Inc.
Ziemer Rita A
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