Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-05-08
2003-03-18
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000
Reexamination Certificate
active
06535439
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuit memory devices, and in particular to a memory device having open digit line architecture.
BACKGROUND OF THE INVENTION
A memory device such as a dynamic random access memory (DRAM) device typically comprises a number of memory cells arranged in rows and columns. The memory cells are grouped into sub-arrays. Each memory cell includes a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The access transistors of the memory cells connect to internal signal lines, referred to as bit or digit lines. The digit lines connect to input/output lines through input/output transistors, which are used as switching devices to allow data to be transmitted between the digit lines and the input/output lines during a read or write mode.
A number of sense amplifiers are included in the memories to both sense data stored in the memory cells and amplify the data for outputting. Each sense amplifier compares a charge stored on a memory cell with a known reference. A sense amplifier typically connects to two digit lines to perform the sensing operation. In the sensing operation, the two digit lines are first equalized to a reference voltage which is typically, but not limited to, one half of the supply voltage (Vcc). After that, the digit lines are driven to opposite voltage levels. That is, one of the digit lines is driven to Vcc and the other is driven to ground. The voltage on the digit line connected to the memory cell being accessed indicates the value of data stored in the memory cell.
In a memory device having an open digit line architecture, the sense amplifiers are located between the sub-arrays. Each sense amplifier connects to two digit lines, which connect to memory cells from two adjacent sub-arrays. However, the sense amplifiers located at the sub-array at the edge of the memory array (edge sense amplifiers), only connect to memory cells from the edge sub-array on one side. The other digit line does not connect to any memory cells because there is no sub-array on the other side of the edge sense amplifiers. Thus, edge sense amplifiers are not used. These are just dummy sense amplifiers. The memory cells connected to the edge sense amplifiers are, therefore, dummy memory cells. The digit lines connected to the dummy sense amplifiers are dummy memory cells. In the conventional memory device having an open digit line architecture, the dummy digit lines always connect to a fixed voltage, typically Vcc/2.
In the open digit line memory device, all digit lines are interleaved. That is one digit line of a sub-array connects to one sense amplifier on one side of the sub-array, and an adjacent digit line connects to another sense amplifier on the other side of the sub-array. Therefore, the edge sub-array has dummy digit lines being interleaved with the normal digit lines. That is every dummy digit line is adjacent to two normal digit lines and every normal digit line is adjacent to two dummy digit lines.
A problem arises when a stress test is applied to the sub-arrays of memory cells of the traditional open digit architecture memory device. During the test, a test pattern is applied to the memory cells. The test pattern may be set to include random data, which is represented by different voltages such as Vcc and ground. For example, opposite voltages of Vcc and ground can be written to two adjacent memory cells. Writing a test pattern of Vcc and ground to the memory cells during the test is similar to writing data having logic “1” and logic “0” to the memory cells during a normal memory operation. This way, the digit lines connected to the memory cells can be driven to the opposite voltages of Vcc and ground to stress for any defect between the digit lines or between the memory cells.
However, because the dummy memory cells of the traditional open digit line memory device always connect to Vcc/2, the voltages between a normal digit line and an adjacent dummy digit line can only be Vcc and Vcc/2 or ground and Vcc/2. This means that the memory cells or digit lines of the edge sub-arrays only get half the stress of that of the memory cells or digit lines of the non-edge sub-arrays. Therefore, in the traditional open digit line memory device, the test may not detect a defect that occurs at the edge sub-arrays when the same defect could have been detected had it occurred at the non-edge sub-arrays.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved open digit line memory device in which memory cells including the memory cells of the edge sub-arrays can be equally tested.
SUMMARY OF THE INVENTION
The present invention includes a memory device having a plurality of sub-arrays of memory cells connected to a plurality of digit lines. A portion of the digit lines are dummy digit lines, which always connect to a fixed voltage during a normal mode. However, according to the teaching of the invention, during a test, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays can be equally stressed during the test.
In one aspect, the memory device includes a plurality of normal memory cells and dummy memory cells. The normal memory cells connect to normal digit lines. The dummy memory cells connect to dummy digit lines. The dummy digit lines always connect to a fixed voltage during a normal mode. The memory device further includes a voltage controller. The voltage controller replaces the fixed voltage with a variable voltage during a test.
In another aspect, a method of testing a memory device is provided. The method includes activating a test mode signal during a test. The method also includes disconnecting a fixed voltage connected to a voltage bus. The voltage bus connects to a plurality of dummy digit lines of a sub-array of memory cells. The sub-array is located at an edge of a memory array of the memory device. The method further includes applying a variable voltage to the voltage bus during the test.
REFERENCES:
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 6222752 (2001-04-01), Kumar et al.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Tran M.
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