Digital phase lock loop circuit

Details Digital phase lock loop circuit Digital phase lock loop circuit

1999-12-28

2003-09-30

Vo, Don N. (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000

Reexamination Certificate

active

06628739

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a digital phase lock loop circuit for phase synchronizing of clock signals for data transmission, and more particularly to a digital phase lock loop circuit with a reduced consumed current.
The digital phase lock loop circuit multiplies a reference frequency of a reference clock signal to generate a synchronous signal which synchronizes with the reference clock signal.
FIG. 1
is a block diagram illustrative of a conventional digital phase lock loop circuit. The conventional digital phase lock loop circuit is connected to an input circuit
101
. The input circuit
101
receives an external clock signal CK to generate an internal reference clock signal CKin on the basis of the external clock signal CK. The conventional digital phase lock loop circuit receives the internal reference clock signal CKin from the input circuit
101
. The conventional digital phase lock loop circuit comprises a delay line
102
, a timing generator circuit
103
, a phase comparator
104
and a delay control circuit
105
.
The delay line
102
is connected to the input circuit
101
for receiving the internal reference clock signal CKin from the input circuit
101
, so that the delay line
102
adds a delay value to the internal reference clock signal CKin to output the same from an output terminal OUT. The timing generator circuit
103
is also connected to the input circuit
101
for receiving the internal reference clock signal CKin from the input circuit
101
, so that the timing generator circuit
103
outputs a delay control enable signal “EN” at a predetermined timing and also outputs a phase comparison enable signal “FCE” for every constant cycles. The phase comparator
104
is also connected to the input circuit
101
for receiving the internal reference clock signal CKin from the input circuit
101
. The phase comparator
104
is also connected to the timing generator circuit
103
for receiving the phase comparison enable signal “FCE” from the timing generator circuit
103
. The phase comparator
104
is also connected to an output side of the delay line
102
for receiving a feed-back clock signal “FBC”. The phase comparator
104
compares phases of the internal reference clock signal CKin and the feed-back clock signal “FBC” upon receipt of the phase comparison enable signal “FCE”, so as to generate a phase comparison signal “PCS”.
The delay control circuit
105
is connected to the timing generator circuit
103
for receiving the delay control enable signal “EN” from the timing generator circuit
103
. The delay control circuit
105
is also connected to the phase comparator
104
for receiving the phase comparison signal “PCS” from the phase comparator
104
. The delay control circuit
105
generates a delay control signal “DCO” on the basis of the phase comparison signal “PCS” upon receipt of the delay control enable signal “EN”. The delay control circuit
105
is also connected to the delay line
102
for sending the delay control signal “DCO” to the delay line
102
, so that if the timing of the feed-back clock signal “FBC” is early, the delay line
102
is delayed, and if the timing of the feed-back clock signal “FBC” is delay, the delay line
102
is accelerated, whereby the feed-back clock signal “FBC” is made correspond to the internal reference clock signal CKin and then locked. After the feed-back clock signal “FBC” has been locked, then alternating acceleration and delay operations of the feed-back clock signal “FBC” are made by the delay line
102
.
FIG. 2
is a timing chart illustrative of waveforms in operations of the conventional digital phase lock loop circuit of
FIG. 1. A
comparative cycle T
1
is set to correspond to four clocks of the internal reference clock signal CKin. In the comparative cycle T
1
, the delay control signal “DCO” is outputted so that a switching operation of the delay line
102
is conducted. Operations of outputting the phase comparison enable signal “FCE” from the timing generator circuit
103
for every four clocks of the internal reference clock signal CKin and operations of outputting the delay control signal “DCO” from the delay control circuit
105
for the comparative cycle T
1
are sequentially conducted.
If the phase lock loop circuit is mounted on a dynamic random access memory, then the above output operation is executed normally even in the pre-charge stand-by after the locking and outputting a signal representing the self-refresh. In case of DRAM, if the read out and write operations are normally executed, in the pre-charge stand-by or self-refresh, no read out operation nor write operation is executed whereby a consumed current is reduced. For example, a note type personal computer is operable by a battery as a power. During no operation of the read or write operation, almost no current consumption is made to prolong a life-time of the battery.
In recent years, the semiconductor device with the DRAM is likely to accommodate the digital phase lock loop circuit in response to the requirement for accurate data transmissions. In this circumstances, the digital phase lock loop circuit has been improved to shorten the necessary time for locking the signal and for reduction in fluctuation. However, the digital phase lock loop circuit is usually operated in the pre-charge stand-by state or self-refresh operation even the current consumption may further be reduced.
In the above circumstances, it had been required to develop a novel digital phase lock loop circuit free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel digital phase lock loop circuit free from the above problems.
It is a further object of the present invention to provide a novel digital phase lock loop circuit which is capable of reducing a current consumption in a pre-charge stand-by state or a self-refresh operation.
The present invention provides a digital phase lock loop circuit having a phase comparator for comparing a reference clock signal with a reference frequency to a synchronous signal generated on the basis of the reference frequency to output an output signal representing a comparison result, a delay control system connected to the phase comparator for receiving the output signal from the phase comparator to control a delay of the synchronous signal in accordance with the output signal, wherein an input circuit is further provided which is connected to an input side of the phase comparator so that the reference clock signal is inputted through the input circuit to the phase comparator, and the input circuit discontinues the input of the reference clock signal to the phase comparator upon receipt of a discontinuation signal.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.


REFERENCES:
patent: 5574757 (1996-11-01), Ogawa
patent: 5973525 (1999-10-01), Fujii
patent: 5990730 (1999-11-01), Shinozaki
patent: 6154071 (2000-11-01), Nogawa
patent: 64-20724 (1989-01-01), None
patent: 2-162834 (1990-06-01), None
patent: 6-85663 (1994-03-01), None
patent: 8-147967 (1996-06-01), None
patent: 9-293374 (1997-01-01), None
patent: 10-224215 (1998-08-01), None
Korean Office Action dated Feb. 26, 2003 with partial English translation.

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