Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2000-03-15
2003-05-20
Talbot, Brian K. (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S097100, C427S250000, C427S255110, C427S124000
Reexamination Certificate
active
06565917
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a screening paste, and more particularly to a platible non-metallic filler material for use in metallurgical screening pastes used in a via structure for a ceramic electronic packaging or used in forming an external feature such as an input/output (I/O) pad, tab, wire band pad, sealed band, lines, and the like.
DESCRIPTION OF THE RELATED ART
In the ceramic electronic packaging technology, a problem may arise if a via structure is placed too closely to another via structure on the top or bottom of a substrate, and where the via diameter is greater than a predetermined size for the separation distance. Specifically, a radial crack may propagate between the two vias.
To maximize the utility of any substrate, a designer will pack electronic features as closely together as possible. However, ground rules must be established that maintain appropriate distances such that cracks will not form and propagate between vias.
In addition to maintaining appropriate spacing, another technique to avoid via-to-via cracks has been to include “stress relief vias” in the design. These vias are designed to preferentially crack and relieve stress so that “live” vias in the matrix do not crack.
However, a problem with stress relief vias is that they take up valuable “chip real estate” on the design surface without providing any electronic function. Therefore, the designer is limited by having to include stress relief vias in the design and loses chip space which otherwise would be available for other components and functions.
In an attempt to minimize potential cracks to be initiated and propagate between vias, one approach has been to include in the via the metallurgical paste constituents that alter the overall effective thermal coefficient of expansion (TCE) of the via, such that it more closely approximates the TCE of the ceramic body of the substrate. Generally, these “filler” materials are high-melting point metal oxides that will not react chemically with the metal particles in the paste (e.g., the via paste) during sintering. Otherwise, such interaction would compromise the final electrical characteristics of the conductive lines and vias in the fired substrate of the chip.
Additionally, generally, the more filler material that is added to the metallurgical paste, the less likely it becomes for via-to-via cracks to form, given that other geometrical arrangements are maintained constant for the comparison.
However, simply adding additional amounts of non-metallics to the metallurgical paste is problematic for several obvious reasons. Specifically, the screenablity of the paste, its final conductivity, densification behavior, etc. are affected by indiscriminately adding additional amounts of non-metallics.
Moreover, one of the main limiting constraints is the platibility of the fired metallurgical paste. Oftentimes, refractory metals such as tungsten and molybdenum are used as the conductive materials for substrate metallization, because of the high sintering temperatures (e.g., about 1500-1600° C. for alumina substrate) required for many ceramics (e.g., especially alumina). Refractory metals such as tungsten and molybdenum can tolerate such high temperatures.
However, a problem arises since refractory metals such as tungsten and molybdenum are not directly brazable or solderable due to their surface wettability. Generally, the external terminal refractory metal features, pads, and vias first must be plated with a metal which is brazable and solderable and which also can be made to bond with molybdenum and tungsten. Usually, nickel is used as the plating metal, and the common processes used for plating external features with nickel are electroplating and electroless plating in a wet bath.
Besides these two common plating processes (e.g., electroplating and electroless plating), a relatively new process has been developed which plates electrolessly a nickel film via a dry chemical vapor deposition (CVD) process. Variations of this method are disclosed in U.S. Pat. No. 4,664,942 and in U.S. Pat. No. 5,869,134, both incorporated herein by reference.
However, for many plating applications of terminal features such as those discussed above, the nickel coating film must cover completely the underlying refractory metal termination, so that even pin holes in the nickel coating film are reduced or eliminated.
Additionally, since the metallurgical paste was purposely formed to contain non-metallics, it is difficult to successfully plate the refractory metal terminations and simultaneously cover completely all the non-metallic non-platible inclusions in the metallurgical paste. This difficulty especially arises in the new CVD process referred to above. Specifically, the CVD deposition tends to grow vertically rather than horizontally, thereby requiring a very thick nickel film deposition, so as to ensure the complete coverage of all non-metallic, non-platible constituents.
Thus, in the conventional methods, a trade-off must be made between: 1) how much non-metallic can be added to a paste so as to reduce via-to-via cracks and improve design; and 2) how much non-metallics must be limited in order to completely cover these non-metallic inclusions during plating.
It is noted that one of the most significant features raising many difficulties is a via, such as a C4 via, which has a very small diameter and tight spacing so as to match an I/O grid of a semiconductor device. It is known that, if any pin holes exist in the nickel film covering the C4 via, then voids in the solder attachment therefor may form. These voids cause reliability problems and reduce the fatigue life of the solder connection between the chip and the substrate.
Thus, the conventional methods result in more restrictive ground rules, the inclusion stress relief vias which take up valuable chip real estate, and/or thicker Ni films which result in various problems.
It is noted that, for example, as the Ni films get thicker, less uniformity results.
Further, in a typical DP nickel plating process, the interface which secures the I/O pads is glass, with “glass fingers” being formed by the glass flowing during the sintering operation. However, the glass is subsequently affected by the iodide atmosphere inherent to the Ni plating operation. Specifically, as thicker Ni films are plated, a greater time is required in a hightemperature environment, and a greater time that the glass is exposed to the iodide atmosphere. The iodide environment attacks the glass fingers. Thus, the glass and its bonding ability are affected by the high temperatures used and associated with the thicker Ni film.
Additionally, thicker films result in greater costs.
Yet another problem is that I/O pad adhesion generally is not optimized in the conventional DP Ni plating process.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional methods and structures, it is a purpose of the present invention to provide a method and structure in which the amount of non-metallics to be added to a paste is optimized so as to reduce via-to-via cracks and improve design, but also so that these non-metallics can be completely covered during plating.
Another purpose is to provide a method and structure in which a via (e.g., a C4 via) having a very small diameter and tight spacing is efficiently produced such that pin holes in a film (e.g., Nickel) covering the C4 via are minimized, and thereby voids in an attachment mechanism (e.g,. solder) are prevented.
Yet another purpose is to provide a method and structure in which a fatigue life of a solder connection between chip and substrate is maintained.
A further purpose is to provide a structure and method which is less costly and provide more design options than providing stress relief vias, and which further provides a high-quality plating with low thickness, and improved ground rules.
In a first aspect of the present invention, a paste for one of a via and an external feature of a ceramic substrate, includes at least one of titania and zirco
Reddy Srinivasa S. N.
Wall Donald R.
International Business Machines - Corporation
Pepper Margaret A.
Talbot Brian K.
LandOfFree
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