Static timing analysis method for a circuit using generated...

Details Static timing analysis method for a circuit using generated... Static timing analysis method for a circuit using generated...

2001-11-16

2003-05-13

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06564360

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89126650, filed Dec. 13, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a static timing analysis method for a circuit using generated clock. Particularly, this invention is directed to a static timing analysis method for flip-flop (FF) or latch, which use generated clock.
2. Description of Related Art
For the software design tools associating with computer auxiliary used in the current integrated circuit design, when the user accomplishes the circuit design, the computer auxiliary design software would proceeds various analyses, so as to ensure that the designed circuit is a circuit which can work properly, wherein a tool of timing analysis is widely used for predicting the performance and accuracy for the circuit.
The timing analysis is generally categorized into two types of dynamic timing analysis and static timing analysis (STA). About the performance of the simulated circuit, the dynamic timing analysis provides the most detailed and accurate related information. However, it takes a long time to simulate. Contrary to the dynamic timing analysis, the STA provides a saving time method to predict the performance of circuit, whereby it can be determined that whether or not the time sequence of circuit is correctly working under design expectation. The STA provides the complete timing path validation, but also fast find out the critical path where timing violation may occur.
Referring to
FIG. 1
, it illustrates a conventional circuit diagram for a logic circuit using STA manner. All the logic circuits connected between the FF
102
and FF
104
are represented as a combinatorial logic circuit
106
. The FF
102
is used for receiving input signal Input
2
and the clock signal Clock
1
, and exporting a signal S
1
to the combinatorial logic circuit
106
. In addition, the combinatorial logic circuit
106
further receives an input signal Input
1
and exports a signal S
2
and an output signal Output
1
. The FF
104
is used to receive the signal S
2
and the clock signal Clock
2
, and export the output signal Output
2
.
The STA is directed to a timing analysis performed on the all signals propagated on the signal propagation paths from the beginning terminal to the last terminal. Any one of the signal propagation paths occurring timing violation is reported. The beginning terminal is referred to an input port or a clock pin and the last terminal is referred to the output port or the signal of the flip-flop. In
FIG. 1
, the signal propagation path includes, for example, the following four paths: (1) signal propagation path between the input signal Input
1
and the output signal Output
1
; (2) signal propagation path between the input signal Input
1
and the signal S
2
; (3) signal propagation path between the signal S
1
and the output signal Output
1
; and (4) signal propagation path between the signal S
1
and the signal S
2
. The STA can be used to verify whether or not the four signal propagation paths satisfy the timing requirement. If the requirement is satisfied, it means that there is no timing violation occurring.
Whiling performing the STA on the circuit shown in
FIG. 1
, the STA can be completely performed, if the clock s CK
1
and CK
2
of the flip-flop
102
and
104
are applied with clock signals clock
1
and clock
2
, which both are a primary clock with regular cycle or a defined clock according to the primary clock. However, when the clock terminal CK
2
of the flip-flop
104
is applied with a clock signal clock
2
as a generated clock, the conventional computer auxiliary design tool then cannot proceed the STA. This is because all the clock signals used in the computer auxiliary design tool for the circuit to be tested by STA have to be well defined, whereby the STA can be proceeded. In other words, the conventional STA needs to use the clock signals that are well defined, such as a clock signal with a fixed frequency and fixed waveform. However, when the clock signal clock
2
is a generated clock, the generated clock is not a well-defined clock signal. The clock signal clock
2
cannot be defined out before the clock signal clock
2
is used to perform the STA. Therefore, when the clock signal the clock
2
is a generated clock, the conventional STA cannot be performed. Thus, the user cannot recognize whether or not a timing violation occurs on the signal path, such as the fourth path, and can only obtain the operation of the circuit by the manner of dynamic timing analysis that is time consuming. Or, the user has to find out the signal paths, which possibly have timing violation. This is also very time consuming and difficult.
In the foregoing, the generated clock means that a clock signal without regular condition, and can come from any clock signal from the combinatorial logic circuit but not from the primary clock or the defined clock from the primary clock.
In
FIG. 1
, if a latch replaces the flip-flop
104
, the clock input terminal of the latch is also a generated clock, the computer auxiliary design tool can also not report which signal path occurs timing violation. Thus, it is very inconvenient for performing the timing analysis.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a static timing analysis method on a circuit using generated clock, so as to solve the issues that the conventional static timing analysis cannot be performed on the a circuit of flip-flop and the latch using generated clock. By the method of the invention, the user can promptly known whether or not the signal path with respect to the flip-flop and latch has timing violation, whereby the correctness of the clock used in the circuit can be judged.
According to the objectives of the invention, the invention provides a method for checking a setup time in a static timing analysis, used to judge whether or not a timing violation occurs on a logic circuit. The logic circuit includes a first sequential logic gate, a second sequential logic gate, a first combinatorial logic circuit, a second combinatorial logic circuit, and a third sequential logic gate. The first sequential logic gate is used to receive a first input signal and a first clock signal, and export a first signal at a first output terminal. The clock signal includes a primary clock or a defined clock based on the primary clock. The second sequential logic gate is used to receive a second input signal and a second clock signal, and export a second signal at a second output terminal. The second clock signal includes a primary clock or a defined clock based on the primary clock. The first combinatorial logic circuit and the second combinatorial logic circuit, respectively, include multiple logic gates. The first combinatorial logic circuit is used to receive the first signal and export a third signal. The second combinatorial logic circuit is used to receive the second signal and export a fourth signal. The third sequential logic gate includes a signal input terminal, a clock input terminal, and a third output terminal. Multiple first signal propagation paths are included between the signal input terminal and the first output terminal, while multiple second signal propagation paths are included between the clock input terminal and the second output terminal. The signal input terminal is used to receive the third signal, and the clock input terminal is used to receive a fourth signal. The third sequential logic gate includes a setup time. The method of checking the setup time includes first finding out a first signal propagation path, which has a maximum sum of propagation delay time of the logic gates. In the foregoing, the maximum one of the sum of propagation delay time of the logic gates is defined as a first maximum delay time. Then, a second signal propagation path with a minimum sum of the propagation delay time of the logic gates is found out. The minimum sum of the propagation delay time of the logic gates is defined as a

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