Matched transistors and methods for forming the same

Details Matched transistors and methods for forming the same Matched transistors and methods for forming the same

2000-03-14

2003-04-22

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000

Reexamination Certificate

active

06552396

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronic circuitry and more particularly to matched transistors and methods for forming the same.
BACKGROUND OF THE INVENTION
Digital and analog circuits often employ transistors having “matched” parameters (i.e., matched transistors). Sense amplifiers, for example, employ matched transistors to optimize circuit performance and to ensure circuit robustness (e.g., as matched transistors are more stable and are less likely to change state during noise events).
Two transistors are matched by ensuring that (1) the transistors have matched physical characteristics (e.g., similar channel lengths, similar channel widths, similar source, drain and channel doping levels, etc.); (2) the transistors have matched electrical characteristics (e.g., similar gains, similar channel resistances, similar threshold voltages, etc.); and (3) the transistors experience similar voltage potentials during operation (e.g., similar gate, source and/or drain potentials, similar body potentials, etc.).
Modern semiconductor device fabrication techniques allow precise control over the doping levels, device geometry and other physical characteristics of metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Therefore, both the physical characteristics and the electrical characteristics of MOSFETs may be easily matched. However, unlike transistors formed on bulk substrates, transistors formed on silicon-on-insulator (SOI) substrates may not behave as matched transistors despite having matched physical and electrical characteristics. Specifically, two SOI transistors having matched physical and electrical characteristics may behave differently (despite being identically biased) due to the effective isolation of each transistor's floating body by fully depleted source/drain junctions (e.g., as each transistor's floating body may reside at a different voltage potential). A need therefore exists for matched SOI transistors and methods for forming such matched SOI transistors.
SUMMARY OF THE INVENTION
To overcome the needs of the prior art, novel matched transistors and methods for forming the same are provided. Specifically, a novel SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width.
The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under another portion of the width of the central diffusion region. Thus, the pair of body regions remain at the same potential during operation of the SOI multiple FET structure. Methods for forming the novel SOI multiple FET structure are also provided.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.


REFERENCES:
patent: 5395778 (1995-03-01), Walker
patent: 5525531 (1996-06-01), Bronner et al.
patent: 5541431 (1996-07-01), Kawashima
patent: 5656845 (1997-08-01), Akbar
patent: 5789781 (1998-08-01), McKitterick
patent: 5801080 (1998-09-01), Inoue et al.
patent: 5994738 (1999-11-01), Wollesen
patent: 6130458 (2000-10-01), Takagi et al.
patent: 6133608 (2000-10-01), Flaker et al.
patent: 6211551 (2001-04-01), Suzumura et al.
patent: 6274896 (2001-08-01), Gibson et al.
patent: 6274907 (2001-08-01), Nakagawa
patent: 6324101 (2001-11-01), Miyawaki
patent: 60180172 (1985-09-01), None
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 2—Process Integration, pp. 680-681; Lattice Press, Sunset Beach, CA (1990) (First Ed.) (ISBN: 0-961672-4-5).*
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 3: The submicron MOSFET, pp. 601-603; Lattice Press, Sunset Beach, CA (1995) (First Ed.) (ISBN: 0-961672-5-3).

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