Queue manager for a buffer

Details Queue manager for a buffer Queue manager for a buffer

2000-01-04

2003-04-29

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Flow controlling

C710S057000, C710S108000, C365S230080

Reexamination Certificate

active

06557053

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to management of queues of data being received from an outside source and inputted into a device for further processing. In more particular aspects, this invention relates to an improved DRAM used in conjunction with a FIFO buffer for controlling the queue of received data.
BACKGROUND OF THE INVENTION
There are many applications in which data is received at a higher rate than it can be utilized by a particular device for short periods of time, thus necessitating queuing data for orderly input into the device on which it is to be used. A common type of queue is first-in, first-out (FIFO) buffers which temporarily store the data being received from some outside source for input into the receiving device at a rate the receiving device can accommodate. One of the problems encountered is that the FIFO buffers may exceed their capacity to store data inputted faster than it can be outputted. Thus, there is a need for a technique for managing data in an orderly way with minimum overhead for periods of time when such data being inputted is greater than the storage capacity of the FIFO buffer or buffers.
SUMMARY OF THE INVENTION
According to the present invention, a bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including a separate DRAM that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage preferably a DRAM and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. The DRAM can be a separate chip, or it can be formed on the ASIC. In either case, its memory is separate from the FIFO buffer or buffers.


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“The SP2 High-Performance Switch” by Stunkel et al, IBM Systems Journal, vol. 34, No. 2, 1995, pp. 185-204.

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