Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating
Reexamination Certificate
2001-12-04
2003-03-25
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Gettering of substrate
By implanting or irradiating
C438S475000, C438S477000
Reexamination Certificate
active
06537896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures having copper-filled trenches and/or vias formed in porous low-k dielectric material. More particularly, the invention relates to an improvement in the process of forming such structures wherein a non-porous dielectric diffusion barrier layer is formed on etched via and trench sidewall surfaces in a layer of porous low k dielectric material by exposing such etched surfaces to a plasma formed from one or more gases to prevent adsorption of moisture and other process gases into the layer of porous low k dielectric material, and to prevent degassing from the porous low k dielectric to material during subsequent processing.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped. silicon oxide, by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of 2.9.
However the replacement of conventional silicon oxide (SiO
2
), having a dielectric constant of about 4.0, with low k dielectric material such as described above, creates problems such as, for example, its higher sensitivity to etchants used in formation of integrated circuit structures. Do This can result in damage to such low k material during the etching of openings therein for formation of vias and trenches. Densification of such non-porous low k dielectric material is known either to repair damage or to enhance the ability of such low k dielectric material to withstand damage from such etchants.
The aforementioned U.S. patent application Ser. No. 09/884,736 by the inventors of this invention teaches the densification of the surface of a layer of a non-porous low k dielectric material to permit formation of a hard mask or an etch stop layer from the resulting densified layer.
Sukharev, Uesato, Hu, Hsia, and Qian U.S. Pat. No. 6,114,259 teaches the treatment of non-porous low k dielectric material to form a densified layer over exposed surfaces of the low k dielectric material prior to the removal of the photoresist etch mask to protect the exposed low k dielectric material from the ashing treatment used to remove the etch mask.
The above-referenced Catabay, Hsai, and Kabansky U.S. Pat. No. 6,346,490, issued Feb. 12, 2002, discloses a process for treating exposed surfaces of non-porous low k dielectric material with an N
2
densification step after the via etch and then treating the via surfaces to a carbon-containing gas after the ashing step to remove the photoresist mask to repair damage caused by removal of the photoresist mask used to form the openings and removal of etch residues.
Another approach to the reduction of capacitance in integrated circuit structures is to further lower the dielectric constant (k) by introducing porosity into the dielectric layer. Porous dielectric materials, and methods of making same, are described, for example, in Rostoker, Pasch, and Kapoor U.S. Pat. No. 5,393,712; Kapoor and Pasch U.S. Pat. No. 5,470,801; Kapoor and Pasch U.S. Pat. No. 5,598,026 (a division of U.S.Pat. No. 5,470,801); and Kapoor and Pasch U.S. Pat. No. 5,864,172 (a continuation of U.S. Pat. No. 5,598,026); all assigned to the assignee of this invention and the subject matter of all of which is hereby incorporated by reference. In these patents, a composite layer is formed on an integrated circuit structure comprising a dielectric material and an extractable material. The extractable material is removed from the composite layer, leaving a porous structure of dielectric material. Other forms of porous low k dielectric material are commercially available.
The above-mentioned shrinking of integrated circuits and the concurrent ever increasing demands for faster speeds, has also resulted in renewed interest in the use of copper as a filler material for vias and contact openings instead of tungsten, as well as for use in metal lines instead of aluminum because of the well known low electrical resistance of copper, compared to either aluminum or tungsten.
But there are negative aspects to the choice of copper for via filling, or in the formation of metal lines. The usual patterning of a blanket-deposited metal layer through a mask to form a pattern of metal lines or interconnects cannot easily be carried out using copper, resulting in the need to first deposit a dielectric layer such as silicon oxide, and then form a series of trenches in the dielectric layer corresponding to the desired pattern of metal lines or interconnects. The trench surfaces are then lined with a diffusion barrier layer or liner (to prevent migration of copper into the dielectric material, as well as to promote adhesion of the filler metal to the trench surfaces), and then filled with copper metal by first forming a copper seed layer over the barrier layer, e.g., by a CVD process, and then filling the remainder of the trench with a blanket deposition of copper, e.g., by a copper plating process.
While the combined use of a porous low-k dielectric material, such as described above, and a copper filler in the trenches and vias etched in such materials can result in the desired reduction in capacitance and enhanced speed, other problems have arisen due apparently to the combined use of a porous dielectric material and a copper filler for the trenches and/or vias etched in such porous dielectric material.
Referring to
FIGS. 1 and 1A
, an integrated circuit structure, denoted as
2
, is shown having a composite layer porous dielectric structure generally indicated at
4
formed thereon comprising a non-porous lower barrier layer
10
of one or more dielectric materials, a porous low k dielectric layer
20
, and an upper layer non-porous barrier layer
30
of one or more dielectric materials. An opening
40
is shown formed through dielectric layers
10
,
20
and
30
to form a trench or via opening in composite layer structure
4
.
Formation of such an opening
40
through layers
10
,
20
, and
30
often results in the opening of one or more pores, such as illustrated pore
22
, in porous low k dielectric layer
20
, resulting in the formation of pointed edges
24
remaining on the punctured or ruptured pore
22
, as best seen in FIG.
1
A. When a subsequent barrier liner layer
50
, of e.g. tantalum metal, is then formed as
Catabay Wilbur G.
Hsia Wei-Jen
Jr. Carl Whitehead
LSI Logic Corporation
Schillinger Laura
Taylor John P.
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