Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-25
2003-05-20
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S344000, C257S350000, C257S408000
Reexamination Certificate
active
06566711
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an active-matrix electro-optical device and, more particularly, to a field-effect transistor which can be applied to an active-matrix liquid crystal electro-optical device or the like and has definite switching characteristics. Also, the invention relates to a method of fabricating such a field-effect transistor.
BACKGROUND OF THE INVENTION
The prior art thin-film insulated-gate field-effect transistor used in an active-matrix liquid-crystal electro-optical device is constructed as shown in
FIG. 2. A
blocking layer's is formed on an insulating substrate
9
. A semiconductor layer having a source
4
, a drain
5
, and a channel region
3
is formed on the blocking layer
8
. A gate-insulating film
2
and a gate electrode
1
are laminated on the semiconductor layer. An interlayer insulating film
12
is formed on the gate-insulating film
2
and on the gate electrode
1
. A source electrode
6
and a drain electrode
7
are formed on the interlayer insulating film
12
and on the semiconductor layer.
This prior art insulated-gate FET is manufactured in the sequence described now. First, the blocking layer
8
is formed on the glass substrate
9
by sputtering while using SiO
2
as a target. Then, the semiconductor layer is formed by plasma-assisted CVD and patterned to form the semiconductor layer which will have the source, drain, and channel region. Then, silicon oxide is sputtered to form the gate-insulating film
2
. Subsequently, an electrically conductive layer which is heavily doped with phosphorus and used to form the gate electrode is formed by low pressure CVD. The conductive layer is then patterned to form the gate electrode
1
. Thereafter, dopant ions are implanted while using the gate electrode as a mask, so that the source
4
and the drain
5
are fabricated. Then, the laminate is thermally treated to activate it.
In the insulated-gate FET fabricated in this way, the length of the gate electrode
1
taken in the longitudinal direction of the channel is substantially identical with the channel length, indicated by
10
. In the case of the n-channel structure, the current-voltage characteristic of the FET of this structure is shown in FIG.
3
. This FET has the disadvantage that in the reverse bias region
13
, the leakage current increases with increasing the voltage applied between the source and drain. Where this device is used in an active-matrix liquid-crystal electro-optical device, if the leakage current increases in this way, the electric charge stored in a liquid crystal
29
by a writing current
30
is discharged as a leakage current
31
through the leaking portion of the device during the non-writing period, as shown in FIG.
5
(A). In this manner, it has been impossible to obtain good contrast.
A conventional method of solving this problem is to add a capacitor
32
for holding electric charge, as shown in FIG.
5
(B). However, in order to form such capacitors, capacitive electrodes made of metal interconnects are needed. This results in a decrease in the aperture ratio. Also, it is reported that the aperture ratio is improved by fabricating the capacitors from transparent electrodes of ITO. Nonetheless, this scheme necessitates an excess process and hence has not enjoyed popularity.
Where only one of the source and drain of this insulated-gate FET is connected with a capacitive device or a capacitor and this transistor is used as a switching device, e.g., in the case of a well-known dynamic random access memory (DRAM) of the
1
transistor/cell type or in the case of an active liquid crystal display having pixels each of which has the circuit shown in FIG.
5
(A) or
5
(B), it is known that the voltage at the capacitor device is varied by the existence of a parasitic capacitance between the gate electrode and the drain or source.
The variation V in this voltage is in proportion to the gate voltage V
G
and to the parasitic capacitance and is in inverse proportion to the sum of the capacitance of the capacitive device and the parasitic capacitance. Therefore, it is customary to fabricate the transistor by the self-aligning technology to reduce the parasitic capacitance, thus suppressing variations in the voltage. However, as the dimensions of devices decrease, the contribution of the parasitic capacitance becomes so large that it can no longer be neglected even if the self-aligning process is exploited.
In an attempt to reduce the variation V, a new method has been proposed. In particular, as shown in FIG.
5
(B), a capacitor other than the proper capacitive device is connected in parallel to increase the apparent capacitance of the capacitive device. As described previously, however, the increase in the area of the capacitor cannot be neglected for DRAMs. The decrease in the numerical aperture cannot be neglected for liquid-crystal displays.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an insulated-gate FET free of the foregoing problems.
The above object is achieved by an insulated-gate FET in which the channel length, i.e., the distance between the source region and the drain region, is made larger than the length of the rate electrode taken in the longitudinal direction of the channel (the direction of the channel length), whereby offset regions are formed in those portions of the channel regions which are in contact with the source and drain regions, respectively. The offset regions undergo no or very weak electric field from the gate electrode. The current-voltage characteristic of this device is shown in FIG.
4
.
It is another object of the invention to provide a method for forming the insulated-gate FET described in the preceding paragraph.
Other objects and features of the invention will appear in the course of the description thereof which follows.
REFERENCES:
patent: 3798752 (1974-03-01), Fujimoto
patent: 3838209 (1974-09-01), Tsuchiya et al.
patent: 3955187 (1976-05-01), Bigelow
patent: 4021607 (1977-05-01), Amano
patent: 4068020 (1978-01-01), Reuschel
patent: 4103297 (1978-07-01), McGrievy et al.
patent: 4239346 (1980-12-01), Lloyd
patent: 4365013 (1982-12-01), Ishioka et al.
patent: 4378417 (1983-03-01), Maruyama et al.
patent: 4420870 (1983-12-01), Kimura
patent: 4427978 (1984-01-01), Williams
patent: 4466172 (1984-08-01), Batra
patent: 4468855 (1984-09-01), Sasaki
patent: 4528480 (1985-07-01), Unagami et al.
patent: 4591892 (1986-05-01), Yamazaki
patent: 4597160 (1986-07-01), Ipri
patent: 4597637 (1986-07-01), Ohta
patent: 4600274 (1986-07-01), Morozumi
patent: 4646426 (1987-03-01), Sasaki
patent: 4648691 (1987-03-01), Oguchi et al.
patent: 4649432 (1987-03-01), Watanabe et al.
patent: 4650543 (1987-03-01), Kishita et al.
patent: 4653862 (1987-03-01), Morozumi
patent: 4660030 (1987-04-01), Maezawa
patent: 4670765 (1987-06-01), Nakamura et al.
patent: 4680580 (1987-07-01), Kawahara
patent: 4716403 (1987-12-01), Morozumi
patent: 4727044 (1988-02-01), Yamazaki
patent: 4740829 (1988-04-01), Nakagiri et al.
patent: 4742346 (1988-05-01), Gillette et al.
patent: 4743096 (1988-05-01), Wakai et al.
patent: 4752774 (1988-06-01), Clerc et al.
patent: 4755865 (1988-07-01), Wilson et al.
patent: 4770502 (1988-09-01), Kitazima et al.
patent: 4818077 (1989-04-01), Ohwada et al.
patent: 4818981 (1989-04-01), Oki et al.
patent: 4838654 (1989-06-01), Hamaguchi et al.
patent: 4841294 (1989-06-01), Clerc
patent: 4860069 (1989-08-01), Yamazaki
patent: 4862237 (1989-08-01), Morozumi
patent: 4873516 (1989-10-01), Castleberry
patent: 4888305 (1989-12-01), Yamazaki et al.
patent: 4891330 (1990-01-01), Guha et al.
patent: 4897360 (1990-01-01), Guckel et al.
patent: 4897639 (1990-01-01), Kanayama
patent: 4905066 (1990-02-01), Dohjo et al.
patent: 4916090 (1990-04-01), Motai et al.
patent: 4938565 (1990-07-01), Ichikawa
patent: 4943837 (1990-07-01), Konishi et al.
patent: 4949141 (1990-08-01), Busta
patent: 4959700 (1990-09-01), Yamazaki
patent: 4960719 (1990-10-01), Tanaka et al.
patent: 4969025 (1990-11-01), Yamamoto et al.
patent: 4969031 (1990-11-01), Kobayash
Hiroki Masaaki
Mase Akira
Nemoto Hideki
Takemura Yasuhiko
Uochi Hideki
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
Wilson Allan R.
LandOfFree
Semiconductor device having interlayer insulating film does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having interlayer insulating film, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having interlayer insulating film will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3010551