Method of fabricating system on chip device

Details Method of fabricating system on chip device Method of fabricating system on chip device

2002-01-16

2003-09-02

Le, D (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

C438S552000, C438S558000, C438S671000, C438S587000

Reexamination Certificate

active

06613655

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 90129155, filed Nov. 26, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating an integrated circuit device. More particularly, this invention relates to a method of fabricating a system on a chip device.
2. Description of the Related Art
Due to the great demand for forming light, thin, short, small and multifunctional devices, the fabrication process has been developed from 0.6 micron to 0.35 micron, and to the current 0.18 micron. As the dimension of the device shrinks, the area of the wafer enlarges and the product yield enhances, to fabricate thousands of logic gate circuits on a single chip have been achieved in practical application.
In a system on a chip device, the conventional chip set system is replaced by implementing all the functions of the chip sets into a single chip. However, although the current fabrication process has overcome the limitations of the logic gate number and the product yield, several conventional fabrication processes are now inapplicable.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a system on a chip. The embedded logic, hybrid circuit and memory can be integrated in the same chip. In addition, the invention provides a method of fabricating a system on a chip with simplified process using less photomasks.
In the method provided by the invention, on a substrate having a memory cell region and a peripheral circuit region a gate oxide layer, a polysilicon layer and a dielectric layer are formed. The dielectric layer over the memory cell region is removed. A conductive layer and a cap layer are formed over the substrate. A photoresist layer is formed on the cap layer to cover a region in the memory cell region predetermined for forming a gate and a region in the hybrid circuit region of the peripheral circuit region predetermined for forming a top electrode of a capacitor. Using the photoresist layer as a mask and the dielectric layer and the gate oxide layer as stop layers, the cap layer and the conductive layer over the hybrid circuit region uncovered by the photoresist layer are removed. Meanwhile, the cap layer in the memory cell region uncovered with the photoresist layer and the underlying conductive layer and polysilicon layer are also removed. Consequently, the top electrode of the capacitor and the gates of the memory device are formed. Another photoresist layer is further formed to cover the whole memory cell region, a region in a logic device region in the peripheral circuit region predetermined for forming a gate, and a region in the hybrid circuit region predetermined for forming a bottom electrode. The exposed dielectric layer and the underlying polysilicon layer are etched until the gate oxide layer is exposed. The photoresist layer is then removed. As a result, gates are formed in the memory cell region, the logic circuit region and a capacitor is formed in the hybrid circuit region.
In addition, a first well, a second well and a third well are formed in the memory cell region, the logic device region and the hybrid circuit region, respectively. The doping concentration of the first well is lower than those of the second and the third wells. The conductive layer comprises a metal silicide layer or a polycide layer. The cap layer is made of silicon nitride or silicon oxy-nitride.
In the above method, the gate in the memory cell region and the top electrode in the hybrid circuit region are formed in the same step, and the gate in the logic device region and the bottom electrode are also formed in the same step. Therefore, the total photomask for forming such device is reduced, so that the fabrication process steps are reduced, and the fabrication cost is lowered.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.


REFERENCES:
patent: 6331462 (2001-12-01), Kasaoka et al.

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