Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2001-06-08
2003-01-14
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S904000, C365S154000
Reexamination Certificate
active
06507124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
It is preferable for the hand-carry type equipment to be reduced in size. Therefore, the memory size of the SRAMs must be reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device includes: a memory cell including a first driver transistor of a first conduction type, a second driver transistor of a first conduction type, a first load transistor of a second conduction type, a second load transistor of a second conduction type, a first transfer transistor of a first conduction type and a second transfer transistor of a first conduction type; a well contact region of a first conduction type; and a well contact region of a second conduction type. The memory cell, the well contact region of the first conduction type, and the well contact region of the second conduction type are provided in a plurality, respectively. The memory cell is equipped with first and second gate electrode layers, first and second drain-drain connection layers, and first and second drain-gate connection layers. The first gate electrode layer includes gate electrodes of the first driver transistor and the first load transistor. The second gate electrode layer includes gate electrodes of the second driver transistor and the second load transistor. The first drain-drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor. The second drain-drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor. The first drain-gate connection layer connects the first drain-drain connection layer and the second gate electrode layer. The second drain-gate connection layer connects the second drain-drain connection layer and the first gate electrode layer. The drain-gate connection layers, the drain-drain connection layers, and the gate electrode layers are provided in different layers, respectively, in plan view. The first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer. The well contact region of the first conduction type is provided for each specified number of memory cells arranged in a first direction. The well contact region of the second conduction type is provided for every two of memory cells arranged in a second direction, which is perpendicular to the first direction.
The present invention is equipped with gate electrode layers that become gates of inverters, drain-drain connection layers that connect drains of the inverters, and drain-gate connection layers that connect gates of one of the inverters and drains of the other of the inverters. In accordance with the present invention, three layers (gate electrode layers, drain-drain connection layers, and drain-gate connection layers) are used to form flip-flops. Accordingly, patterns in each layer can be simplified (for example, into linear patterns) compared to the case in which flip-flops are formed using two layers. In this manner, in accordance with the present invention, since the patterns in each layer can be simplified, a miniaturized semiconductor memory device with its memory cell size being 4.5 &mgr;m
2
or smaller, for example, can be manufactured.
Also, in accordance with the present invention, in plan view, the first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer. As a result, the source contact layer of the driver transistors can be disposed in the central area of the memory cell. Furthermore, wirings that connect the source contact layers to the grounding line can be disposed in the same layer as the drain-drain connection layers and in the center of the memory cell. Accordingly, the degree of freedom in forming the first and second drain-gate connection layers increases. This also facilitates reducing memory cell size. It is noted that, in the present invention, the source contact layer is a conduction layer that is used to connect a source region of the driver transistor to a wiring layer.
Also, in accordance with the present invention, latch-up is prevented. In other words, in a semiconductor memory device in accordance with the present invention, a well contact region can be disposed in a second conduction type well in which driver transistors and transfer transistors are formed for every two memory cells arranged in the second direction. Generally, when the transistors are operated and drain current flows, substrate current (current from an end of the drain to the well contact region) flows. In particular, the driver transistors have the largest substrate current. An increase in the potential that is the product of the substrate current and the substrate resistance (well resistance) causes latch-up. In the structure described above, a well contact region is formed in the memory cell, such that the driver transistor having a large substrate current is located close to the well contact region. As a result, the substrate resistance can be reduced, and therefore the generation of latch-up can be prevented.
Also, in accordance with the present invention, each one of the well contact regions of the second conduction type, which is disposed for every two of the memory cells arranged in the second direction, is disposed for every one of the memory cells arranged along the first direction. The first direction is the direction of the word lines. In general, when one of the word lines is selected, all of the memory cells connected to the word line are operated. In the driver transistors of the selected memory cells, drain current flows at once, and substrate current is generated at once. In accordance with the present invention, a well contact region per each cell is disposed for every one of the memory cells that are operated. As a result, the substrate resistance at all of the driver transistors in operation is lowered, and therefore the latch-up can be prevented. On the other hand, a well contact region is formed for each predetermined number of memory cells arranged in the first direction in the well of the first conduction type where the load transistors are formed. The predetermined number is, for example, 32 or 64. The load transistors only maintain a high potential at cell nodes, and direct current does not flow through the load transistors unlike the driver transistors, such that its substrate current is small. Therefore, for example, when the well contact region of the first conduction type is provided for every 32 cells, and the well resistance becomes large (in particular, a memory cell located intermediate of one well contact region and another well contact region has the largest well resistance), latch-up does not occur.
In accordance with the present invention, the first conduction type and the second conduction type may be set as follows. For example, the first conduction type is n-type and the second conduction type is p-type. Alternatively, the first conduction type is p-type, and the second conduction type is n-type. In a semiconductor memory device in accordance with the present invention, the first conduction type may preferably be n-type and the second conduction type may preferably be p-type. With this structure, an n-type well contact region is provided for each specified number of memory cells arranged in the first direction, and a p-type w
Kodaira Satoru
Kumagai Takashi
Noda Takafumi
Takeuchi Masahiro
Oliff & Berridg,e PLC
Seiko Epson Corporation
Tran Long
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