Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-16
2003-07-29
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S058000, C257S062000, C257S354000
Reexamination Certificate
active
06600196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a thin film transistor that is used in liquid crystal displays of the active matrix system, and a method for manufacturing such a thin film transistor.
2. Prior Art
In a liquid crystal display of the active matrix system that uses thin film transistors, liquid crystals are sealed between a TFT array substrate and a counter substrate overlapping the TFT array substrate with a certain distance. On the TFT array substrate, gate electrodes (Y electrodes) and data electrodes (X electrodes) are arranged as a matrix, and thin film transistors (TFTs) are disposed on the intersections of the gate electrodes and the-data electrodes. The thin film transistors control the voltage impressed to the liquid crystals, and the electrooptic effect of the liquid crystals is utilized to enable displaying.
FIGS. 7A and 7B
are diagrams illustrating the structure of a top-gate type thin film transistor. Conventionally known structures of thin film transistors are a top-gate (positive-stagger) type structure and a bottom-gate (inverse-stagger) type structure. The structure of a top-gate type thin film transistor will be described referring to FIG.
7
A. The top-gate type thin film transistor comprises a light-shield film
102
provided on an insulating substrate
101
such as a glass substrate, on which an insulating film
103
comprising silicon oxide, SiO
x
, or silicon nitride, SiN
x
, is formed. Above the insulating film
103
, a drain electrode
104
and a source electrode
105
composed of ITO (indium tin oxide) films are disposed of a predetermined channel distance. An amorphous silicon film (a-Si film)
106
, as a semiconductor film, that covers both electrodes is provided; a gate insulating film
107
comprising SiO
x
or SiN
x
, is provided above the a-Si film
106
; and a gate electrode
108
is provided above the gate insulator film
107
, to form an island-shaped region called an a-Si island.
As a process for the manufacture of such a thin film transistor, a process known as 7-PEP (PEP: photo engraving process) structure is generally present. In this 7-PEP structure, after a drain electrode
104
and a source electrode
105
composed of ITO film have been patterned, an a-Si film
106
is formed by CVD (chemical vapour deposition), and is patterned in an island shape. A gate insulating film
107
is then formed by CVD, and is patterned to a desired shape. After that, a gate electrode
108
, for example of aluminum (Al), is formed by sputtering, and is patterned to complete a TFT.
However, since such a 7-PEP structure required a large number of process steps, a next-generation 4-PEP structure that requires less process steps had been proposed. In the 4-PEP structure, the gate insulating film
107
and the a-Si film
106
underlying the gate electrode
108
are simultaneously etched. That is, the gate electrode
108
, the gate insulating film
107
, and the a-Si film
106
are sequentially etched in one patterning step using the plated pattern of the gate electrode
108
as a mask. The 4-PEP structure excels in that the manufacturing process is shortened.
FIG. 7A
shows the top-gate type thin film transistor produced by the shortened manufacturing process.
Here, if the gate electrode
108
, the gate insulating film
1
.
07
, and the a-Si film
106
are sequentially eteched in one patterning step, the distance between the end of the gate electrode
108
and the source and drain electrodes
105
and
104
is much shortened as shown in FIG.
7
A. That is, this distance is at largest 0.4 &mgr;m, easily causing short-circuiting between the end surface of the gate electrode
108
and the source and drain electrodes
105
and
104
due to surface leakage.
To cope with this problem, the gate electrode
108
is over-etched as shown in FIG.
7
B. That is, by over-etching the gate electrode
108
during patterning, a length of about 1.5 &mgr;m is secured as shown in
FIG. 7B
, and by clearing a distance of 1.9 &mgr;m (about 2 &mgr;m) between the source electrode
105
and the drain electrode
104
, short-circuiting due to surface leakage is prevented.
The present applicant had presented Japanese Patent Application No. 11-214603 as a technique related to this shortened manufacturing process. The present application provides techniques for decreasing the number of process steps required in the manufacturing process of thin film transistors, as well as for preventing the generation of an abnormal potential due to leakage current from other data lines.
Although, it is not related to decrease in the number of process steps at all, the background art, related to the present invention includes Japanese Patent No. 2522364, and Published Unexamined Patent Application Nos. 1-149480 and 4-367276.
As described above, the over-etching of the gate line at the time of forming the gate electrode
108
of a top-gate type TFT, and the island cutting using a resist mask (not shown) for forming the gate electrode
108
(etching of the gate insulating film
107
and the a-Si film
106
) enable the simplificaiton of the process and the prevention of short-circuiting due to surface leakage.
However, it has now been found that the above-described method might result in the occurrence of leakage in the island portion not covered with the gate electrode
108
(floating island).
FIGS. 8A and 8B
are diagrams that illustrate the states where the floating island portion has been formed. The circumference region of the gate electrode
108
shown in
FIGS. 8A and 8
b
is the floating island portion
109
. Although electrodes are normally disposed above and beneath an a-Si film, the gate electrode
108
is not formed above or beneath the a-Si film
106
that constitutes this floating island portion
109
, which unique as the usage of a-Si. Therefore, voltage is not controlled in this floating island portion
109
. That is, the floating island portion
109
is not covered with the gate electrode
108
, and is in the state where portions nearer the end are more difficult to be controlled by the gate voltage of the gate electrode
108
. The detection of leakage paths using OBIC (optically beam induced current) analysis revealed that leakage occurred due to the voltage between the source electrode
105
and the drain electrode
104
at the portion in the floating island
109
between the source electrode
105
and the drain electrode
104
, above which or beneath which the gate electrode
108
is not formed, that is, the hatched area shown in
FIGS. 8A and 8B
. When leakage occurs at the leakage portion
110
, i.e. the hatched area, voltage cannot be controlled between the source electrode
105
and the drain electrode
104
, and the problem such as the discoloration of pixels due to an abnormal voltage has arisen.
Therefore, the present invention is achieved to solve the above technical problems and the object of the present invention is to reduce leakage current in a floating island portion formed in a thin film transistor.
SUMMARY OF THE INVENTION
A thin film transistor to which the present invention is applied comprises a source electrode and a drain electrode disposed above an insulating substrate at a predetermined interval; a semiconductor film disposed in relation to the source and drain electrodes; a gate insulating film overlapping the semiconductor film; and a gate electrode overlapping the gate insulator film. The semiconductor film has a portion which is disposed between the source electrode and the drain electrode, and above which or beneath which the gate electrode is not formed. A P-type impurity is implanted into the portion.
This P-type impurity is characterized in being boron ion. Boron ion is one of lightest ions as P-type impurities, and is preferable in that it can be implanted into a semiconductor film with a high power. Especially when boron ion is implanted into the semiconductor film from the top of a gate insulating film the light boron ion is preferable because it must be implanted into the semiconductor film through this gate i
Miyamoto Takashi
Morooka Mitsuo
Tokuhiro Osamu
Tsujimura Takatoshi
Eckert George
International Business Machines - Corporation
Jennings, Esq. Derek S.
Scully Scott Murphy & Presser
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