Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-18
2003-03-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S688000
Reexamination Certificate
active
06528414
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to manufacturing methods for semiconductor devices and semiconductor devices, and more particularly to methods of forming wiring layers and wiring line structures. Preferred embodiments of the present invention relate to methods of forming a wiring layer which is formed on an interlayer insulating layer and is connected to a conductive layer via a through hole and devices having such a structure.
BACKGROUND
With the progress in miniaturization and integration of semiconductor devices, multilayer wiring techniques have been hitherto employed in manufacture of the semiconductor devices. Here, the multilayer wiring techniques mean techniques for forming a wiring layer of a multilayer structure. Recently, the demand for further miniaturization and higher integration of semiconductor devices has been increasing more and more. An improvement of multilayer wiring techniques is essential to meet the above demand. For achieving improved multilayer wiring techniques, it is an important problem to improve the method of forming each wiring layer.
SUMMARY
Preferred embodiments relate to manufacturing methods for semiconductor devices and semiconductor devices, including methods of forming wiring layers and wiring line structures.
One embodiment relates to a method for manufacturing a semiconductor device including forming a conductive layer on or above a substrate and forming, on the conductive layer, an interlayer insulating layer having at least one through hole therein. The method also includes forming a plug in the through hole and forming an underlying layer on the plug and the interlayer insulating layer. A layer including aluminum is formed on the underlying layer, with the aluminum layer being formed at a substrate temperature not lower than 250° C. and under a reduced pressure.
Another embodiment relates to a method for forming a semiconductor device, including forming a conductive layer on or above a substrate and forming, on the conductive layer, an insulating layer having at least one through hole therein. A plug is formed in the through hole and an underlying layer is formed on at least a portion of the plug. A layer comprising aluminum is formed on the underlying layer while maintaining a chamber pressure of not greater than approximately 1 Pa.
Yet another embodiment relates to a method for forming a semiconductor device, including forming a first conductive layer on or above a substrate and forming, on the first conductive layer, an insulating layer having at least one through hole therein. A plug is formed in the through hole and an underlying layer formed on or over at least a portion of the plug and the insulating layer. A second conductive layer is formed on or over the underlying layer while maintaining a chamber pressure of not greater than approximately 5 Pa. The second conductive layer is maintained at a temperature below its melting point while forming the semiconductor device.
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Translation of “Decision of Refusal” for Japanese Patent Application No. 11-204720, dispatch date Apr. 10, 2001.
Konrad Raynes & Victor & Mann LLP
Peralta Ginette
Raynes Alan S.
Seiko Epson Corporation
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