Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-24
2003-09-16
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S532000, C438S251000, C438S252000
Reexamination Certificate
active
06621111
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for forming the same and, more particularly, to a MOS-type capacitor structure that can increase a breakdown voltage between a junction region and a well region, and a method for forming the same.
BACKGROUND OF THE INVENTION
Semiconductor devices commonly include a capacitor that comprises a pair of conductive layers and a dielectric layer therebetween. There are typically two kinds of capacitors that are used in semiconductor devices. One is a metal-insulator-metal (MIM) type capacitor that comprises a pair of separated metal plates and an insulation layer therebetween. The other is a metal-oxide-semiconductor (MOS) type capacitor that comprises a semiconductor substrate, a conductive layer formed thereon, and an insulation layer between the substrate and the conductive layer.
The MIM-type capacitor has desirable characteristics that make it an ideal capacitor for the most part. The MIM-type capacitor offers the advantage of the ability to maintain positive and negative electric charges. However, in the MIM-type capacitor, the insulation layer between the metal plates is formed using a chemical vapor deposition (CVD) technique. Accordingly, the insulation layer of the MIM-type capacitor is formed thicker than that of the insulation layer of the MOS-type capacitor, and it is therefore difficult to precisely adjust its resulting thickness.
In comparison with the MIM-type capacitor, the MOS-type capacitor generally employs a gate oxide layer formed during fabrication of a MOS transistor as the dielectric layer. The gate oxide layer is formed by thermally oxidizing the semiconductor substrate, which is a well-known and stable fabricating technique. Thus, the dielectric layer of the MOS-type capacitor may be formed to a relatively thin thickness and also exhibits improved insulating characteristics.
In another approach, the capacitance of a capacitor is proportional to the respective surface areas of the conductive layers and inversely proportional to the space between the conductive layers, i.e., the thickness of the dielectric layer. Thus, in the case where the dielectric layer is relatively thick, the conductive layers should be formed to have large areas in order to provide sufficient capacitance in the capacitor. In this respect, the MOS-type capacitor is more advantageous, in view of the formation of the thin dielectric layer, as compared with the MIM-type capacitor.
FIGS. 1
,
2
A, and
2
B are a top plan view and cross-sectional views for illustrating the conventional MOS-type capacitor.
FIGS. 2A and 2B
are the cross-sectional views taken along lines
1
-
1
′ and
2
-
2
′ of
FIG. 1
, respectively.
Referring to
FIGS. 1
,
2
A, and
2
B, a device isolation layer pattern
12
is formed at a predetermined region of the semiconductor substrate
10
to define an active region. A lower electrode region
20
is formed in the active region using an ion implantation process. At this time, the lower electrode region
20
serves as one conductive layer of the MOS-type capacitor and crosses the active region in one direction. That is, as shown in
FIG. 2B
, the lower electrode region
20
is in contact with sidewalls of the device isolation layer patterns
12
in one direction (e.g.,
2
-
2
′ direction of FIG.
1
).
A gate oxide layer
14
is disposed on the active region where the lower electrode region
20
is formed. An upper electrode
16
overlaps with the device isolation layer pattern
12
across the gate oxide layer
14
, thereby constituting the other conductive layer of the MOS-type capacitor. In this case, the lower electrode region
20
protrudes, as shown in
FIG. 2A
, toward both sides of the upper electrode
16
. A lightly doped region
22
is then formed in the active region of the both sides of the upper electrode
16
to overlap with an edge of the lower electrode region
20
, which protrudes toward sides of the upper electrode
16
.
At this time, the lower electrode region
20
has a rounded edge
99
similar to an impurity region formed by using a conventional ion implantation process. The rounded edge
99
arises in a region where the lower electrode region
20
is in contact with the device isolation layer pattern
12
. In the event that a voltage is applied to the lower electrode region
20
, an electric field is concentrated at the rounded edge
99
. Thus, a junction breakdown arises at the rounded edge
99
earlier than at the planar bottom surface of the lower electrode region
20
. As a result, the aforementioned conventional capacitor structure suffers from a decrease in the junction breakdown voltage.
With reference to “PHYSICS AND TECHNOLOGY OF SEMICONDUCTOR DEVICES”, pages 191-201, by Andrew S. Grove, published in 1967 by John Wiley & Sons, Inc., the breakdown voltage of the device is influenced by the shape of the lower electrode region
20
as well the impurity concentration in the lower electrode region
20
. According to Grove, to increase the breakdown voltage, it is preferable to lower the concentration of the impurity region and to form the impurity region into a gentle shape.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to provide a MOS-type capacitor using a junction region, of which breakdown voltage is high, as a lower electrode.
It is another feature of the present invention to provide a method for forming the MOS-type capacitor, so as to increase the breakdown voltage of the junction region that is used as the lower electrode.
The present invention provides a capacitor structure of a semiconductor device that includes a lightly doped region formed to overlap with an outer edge of a lower electrode region. The capacitor structure comprises a device isolation layer pattern, an upper electrode, a lower electrode region, and a lightly doped region. The device isolation layer pattern is formed at a predetermined region of the semiconductor substrate to define an active region. The upper electrode is disposed above the active region to expose the active region about the upper electrode. The lower electrode region is formed in the active region below the upper electrode such that the upper electrode is positioned above the lower electrode and within an outer edge of the lower electrode. The lightly doped region is formed in the active region at the outer edge of the lower electrode and the device isolation pattern, such that the lightly doped region overlaps with the outer edge of the lower electrode.
A capacitor dielectric layer may optionally be positioned between the active region and the upper electrode. The lightly doped region is preferably formed to a greater depth than the lower electrode region.
A heavily doped region may be disposed within the lightly doped region. The lightly doped region, the lower electrode region, and the heavily doped region include impurities having a conductivity type that is different than that of the active region.
The present invention also provides a method for forming a capacitor structure of a semiconductor device, which includes forming a lightly doped region that overlaps with an edge of a lower electrode region. The method comprises forming a device isolation pattern in a predetermined region of a semiconductor substrate to define an active region; forming a lower electrode in the active region; forming an upper electrode over the active region positioned above the lower electrode and within an outer edge of the lower electrode; and forming a lightly doped region in the active region adjacent the upper electrode between the outer edge of the lower electrode and the device isolation pattern, wherein the lightly doped region is formed to overlap with the outer edge of the lower electrode.
The method may further comprise forming a capacitor dielectric layer on the active region after forming the lower electrode. In this case, the capacitor dielectric layer is formed by thermally oxidizing the active region.
The lightly doped region is preferably formed deeper than th
Mills & Onello LLP
Quach T. N.
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