Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-10-18
2003-07-15
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C156S345130, C438S692000, C438S959000, C451S005000
Reexamination Certificate
active
06594542
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to a system and method for controlling material removal rates during polishing; and, in particular, for controlling thickness removal during chemical mechanical polishing using detection, statistical estimation, and time series analysis.
BACKGROUND ART
Increasingly, chemical mechanical polishing (CMP) is becoming the methodology of choice to polish certain articles of manufacture that require a desired degree of planarization, such as semiconductor wafers from which chips for integrated circuits are processed. Generally, CMP employs a polishing system for processing such a wafer by polishing on one surface thereof by a procedure which includes engagement of the semiconductor wafer face with a polishing pad and a method of controlling such polishing.
Typically, integrated circuits are provided as “chips”, each of which includes a slice of a flat material that has the specific circuitry. A multiple number of the desired integrated circuits are formed at the same time by etching and coating a disk-shaped semiconductor wafer substrate. The wafer is then diced into flat rectangles which are individually provided with suitable packaging having the necessary leads to electrically access the integrated circuitry. In certain instances a full wafer is used to form a single integrated circuit rather than duplicates of a desired integrated circuit.
The disk-shaped wafer substrates typically are comprised of a monocrystalline semiconductor, such as single crystal silicon. One common method of forming the wafer is to grow a relatively long cylinder or log of a single crystal of the material, and then slice the log (often called a boule) to form the individual disk-shaped wafers.
It is necessary for the formation of various circuits or for other uses of wafers, that the active or front face, e.g., the face of the wafer on which the integrated circuitry is to be formed, be highly polished. (The other side of the wafer is often referred to as the wafer “back” face.)
At the beginning of a chemical mechanical polishing (CMP) step for ILD (inter-layer dielectric) planarization at time t
0
, the difference in top surface height, h
initial
, between the field region and areas of dense device features may be as large as 0.8 to 1.0 micro meter. Pre-CMP semiconductor thickness measurements arc used to determine the polishing time (t
final
) for each wafer based on calibrations established in the development stage. At time t
0
, the polisher starts to remove material, typically at a rate of 1-3 kA/minute, but faster on features that are smaller and isolated, and more slowly on features that are larger or in densely packed areas.
Polishing continues through until time (t
final
) when the wafer is removed from the tool, cleaned, and measured afterwards to confirm that an acceptable final thickness (t
final
) was achieved.
The final thickness measurement is an important moment for CMP metrology. The time (t
final
) is selected from a CMP polisher calibration based on applied pressure, rotation speed, average pad life degradation, pressure, etc., to produce a (t
final
) centered within the allowed semiconductor wafer process window. However, dynamic factors may alter the actual thickness (T
true
) realized at time (t
final
). If the material removed by time (t
final
) exceeds the limit, the wafer must be scrapped or more dielectric must be deposited. If the remaining thickness is excessive, the wafer can be returned to the polisher for rework. This above-described loop characterizes the basic CMP method today.
The CMP process window is defined as the difference between the Upper And Lower Thickness Limits (TUL and TLL). The CMP tool design must completely eliminate malfunctions that can cause large thickness errors.
During semiconductor wafer fabrication, silicon is plasma-etched to form device islands, then thin oxide and silicon nitride layers are deposited. Dielectric material (TEOS) is deposited to fill the spaces between the islands and build up a thick dielectric over-layer. CMP tools then planarize the upper surface of this dielectric layer, eventually polishing through the TEOS and exposing the underlying SiN at some locations. Since SiN has a removal rate several times smaller than oxide, the polishing slows at the exposed locations, allowing slower areas to “catch-up” for improved planarity.
Since the SiN removal rate is smaller but still non-zero, it is important to measure the thickness of the remaining oxide and nitride simultaneously. Otherwise, the remaining SiN layer could become too thin at the location where the polish is fastest.
Other semiconductor wafer CMP operation issues include global planarity which are dominated by the “macro” effects of the polisher pad, wafer head chucking device, polish pad velocity, polishing pad age and conditioning, etc. Uniformity from wafer center to wafer edge is the usual metric. Across-the-wafer uniformity is also influenced by boundary effects at device edges, at the wafer edge. CMP tools must provide thickness measurement that can accommodate custom spaced measurements of chosen length and point density in diameter or radius scan format. CMP operations on semiconductor device features with large spatial separations reveal several surprising effects.
First, an effect known as the “edge effect” can cause a thicker oxide in the outer 5-15 mm of the wafer. The excess thickness can range from 1-4 kA depending on the manner in which the wafer is held in the polishing carrier. A second unexpected effect visible in the figure is the oscillation in thickness across the wafer. This 100-200A variation occurs because the CMP TEOS polishing rate is faster in the kerf area adjacent to the test die than in the kerf intersection areas.
Within-die planarity is influenced by the tendency of CMP to polish smaller, individual features faster, and larger and densely-packed features more slowly. The oxide removal rate over features of 15 micro meter width was 60-80% greater than over features of 65 micro meter width under high throughput conditions. This effect introduces considerable complexity, given the differences in pattern density that occur on IC devices.
CMP processing reaches an asymptotic limit in the microplanarity regime, where polishing occurs largely by smoothing and filling-in between the dense, small features, rather than by direct removal of material from larger spacing.
These effects concerning semiconductor device feature size subsequently drive a subordinate requirement that CMP tools automatically perform a sequence of semiconductor wafer film thickness measurements and manage the data from different semiconductor device features accordingly. Each semiconductor device site job file becomes a chain of individual measurements, each with its own location, measurement recipe, pattern recognition model, and data format.
The semiconductor wafer film thickness measurement data generated may be needed in processing according to device feature type and size, as well as locations on the wafer. The CMP tool operator must simultaneously keep within limits the thickness at the smallest, fastest-polishing feature within the fastest-polishing die on the wafer, and at the largest, slowest-polishing feature in the slowest polishing die on the wafer.
To this end, chemical mechanical polishing machines have been designed to provide the desired semiconductor device film thickness. The machine typically brings the device face of the wafer to be polished into engagement with a polishing surface such as the polishing surface of a pad having a desired polishing material, e.g., a slurry of colloid silica, applied thereto.
The movement between the wafer and the polishing pad provides the polishing As forces. In some instances, this “polishing” is provided primarily for the purpose of making one face flat, or parallel to another face. In this connection, it must be remembered that the wafer itself is microcrystalline and characteristics of this type may be quite important in making the wafer suitable for the production of integ
Applied Materials Inc.
Garland Steven R.
Moser Patterson & Sheridan
Picard Leo
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