Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-04
2003-03-18
Lee, Eddie (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S532000
Reexamination Certificate
active
06534814
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, more particularly to a trench capacitor structure of a DRAM (Dynamic Random Access Memory), and also to a method for manufacturing the structure.
2. Description of the Related Art
An example of a DRAM having a sheath-plate type trench capacitor is known from “Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring” published in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 8, August 1988, and written by Toru KAGA, Yoshifumi KAWAMOTO, Tokuo KURE, Yoshinobu NAKAGOME, Masakazu AOKI, Hideo SUNAMI, Tohachi MAKINO, Nagatoshi OHKI and Kiyoo ITOH.
FIG. 1
is a cross sectional view, showing a conventional sheath-plate type trench capacitor. As is shown in
FIG. 1
, a trench is formed in a semiconductor substrate
21
in contact with a field oxide film
1
. An area which includes a trench inner wall oxide film
4
, a silicon oxide/silicon nitride (SiO
2
/SiN) film
10
, a polysilicon film
14
, a diffusion layer
16
and part of the substrate
21
serves as a gate control diode. When a potential has been applied to the polysilicon film
14
(or to a polysilicon film
11
formed in a deep portion of the trench), a depletion layer grows in the vicinity of a peripheral portion of the trench-inner-wall oxide film
4
, thereby forming an inversion layer such that it extends from the diffusion layer
16
along the outer periphery of the trench. As a result, the amount of a junction leak current between the substrate
21
and the diffusion layer
16
contacting the polysilicon film
14
increases.
To reduce the influence of the potential applied to the polysilicon films
11
and
14
, it is necessary to make the oxide film
4
thick. However, increasing the thickness of the oxide film
4
inevitably reduces the area of a capacitor insulating film and hence the capacitance of the trench capacitor.
In the conventional structure, the potential applied to the polysilicon film filled in the trench increases the junction leak current between the substrate and the diffusion layer contacting the polysilicon film. To avoid this, it is necessary to reduce the capacitance of the capacitor to some extent. Actually, however, the capacitance is excessively reduced since an increase in junction leak current is prevented by increasing the thickness of the trench inner wall oxide film.
SUMMARY OF THE INVENTION
It is the object of the invention to provide a highly reliable semiconductor device having a sufficient trench capacitor capacitance and a small junction leak current, and also provide a method for manufacturing the semiconductor device.
According to an aspect of the invention, there is provided a semiconductor device constituting a DRAM having a trench capacitor, comprising:
a semiconductor substrate of a first conductivity type;
a conductive region of a second conductivity type formed in a surface portion of the semiconductor substrate;
a trench formed in a surface portion of the semiconductor substrate, adjacent to the conductive region;
a first capacitor electrode formed on an inner peripheral surface of the trench and having an upper edge portion located below the conductive region;
an insulating layer having a portion which extends from the upper edge portion of the first capacitor electrode to the conductive region and projects inward of the trench and narrows the diameter of the trench;
a capacitor insulating film coated on the first capacitor electrode; and
a second capacitor electrode filling the trench such that it contacts the capacitor insulating film and is electrically connected to the conductive region.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device constituting a DRAM having a trench capacitor, comprising the steps of:
forming in a semiconductor substrate a trench having a wall surface to be able to be oxidized;
coating a material with an oxidation resistance on the wall surface of the trench except for an upper edge portion thereof; and
oxidizing the upper edge portion of the trench, thereby selectively forming an insulating layer projecting inward of the trench.
In the invention constructed as above, that portion of the insulating layer, which extends from the upper edge portion of the first capacitor electrode to the conductive region and in which junction leak can easily occur, is formed thick such that it projects inward of the trench, thereby interrupting at that portion continuous formation of an inversion layer extending along the outside of the trench.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4792834 (1988-12-01), Uchida
patent: 4794434 (1988-12-01), Pelley, III
patent: 4801988 (1989-01-01), Kenney
patent: 4918502 (1990-04-01), Kaga et al.
patent: 4918503 (1990-04-01), Okuyama
patent: 4967248 (1990-10-01), Shimizu
patent: 5017506 (1991-05-01), Shen et al.
patent: 5309008 (1994-05-01), Watanabe
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5422294 (1995-06-01), Noble, Jr.
patent: 5482883 (1996-01-01), Rajeevakumar
patent: 0 234 891 (1987-09-01), None
patent: 0 287 056 (1988-10-01), None
patent: 62-208659 (1987-09-01), None
patent: 1-192157 (1989-08-01), None
patent: 2-9166 (1990-01-01), None
patent: 02-005467 (1990-01-01), None
patent: 02-128466 (1990-05-01), None
patent: 05-013707 (1993-01-01), None
patent: 05-063155 (1993-03-01), None
patent: 05067749 (1993-03-01), None
Japanese Patent Office, Office Action, Nov. 13, 2001, pp. 1-7, Mailing No. 296444.
Toru Kaga et al; IEEE Transactions on Electron Devices, dated Aug. 8, 1988, vol. 35, No. 8, “Half-VccSheath-Plate Capacitor DRAM Cell With Self-Aligned Buried Plate Wiring” pp. 1257-1263.
Iba Junichiro
Kohyama Yusuke
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Pizarro-Crespo Marcos D.
LandOfFree
Method of manufacturing a semiconductor memory device having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor memory device having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor memory device having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3005624