Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-02-22
2003-05-13
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06564362
ABSTRACT:
FIELD OF THE INVENTION
The present invention in general relates to a method of designing a layout of an LSI chip having boundary scan registers. More particularly, this invention relates to a method of automatically arranging boundary scan registers and automatically making a fan-out adjustment.
BACKGROUND OF THE INVENTION
To design the layout of an LSI chip having boundary scan registers, it is conventionally required to arrange many boundary scan registers connected to I/O cells so that the nets of test signals to the boundary scan registers do not cross one another to prevent operation failure caused by the backflow of test signals or the like from occurring.
In addition, to prevent the occurrence of over-capacity and timing errors after providing wirings, it is required to make such a fan-out arrangement before providing the wirings that the capacity does not exceed output terminal driving capability in the connection between a test control circuit and the boundary scan registers. In the fan-out arrangement, it is necessary to arrange a minimum number of buffer cells at optimum positions with a view of reducing an LSI area and wiring jam.
The arrangement of the boundary scan registers is automatically made using a commercially available test circuit synthetic tool. According to this tool, the boundary scan registers are arranged to be attracted to the cells of an internal logic circuit of the LSI. With respect to the fan-out arrangement, according to the above-stated tool, such excessive fan-out as not to cause over-capacity and timing errors is determined and a fan-out arrangement is uniformly made based on the determined excessive fan-out.
FIG. 1
is a typical view of the result of the automatic arrangement of boundary scan registers using a conventional test circuit synthetic tool. In
FIG. 1
, legend
1
denotes an entire LSI, legend
11
denotes an I/O region, a hollow rectangle provided with legend
12
denotes an I/O connection boundary scan register connected to an I/O cell, and a hollow rhombi provided with legend
13
denotes an output I/O control boundary scan register connected to the I/O connection boundary scan register
12
.
According to the conventional boundary scan register arrangement method stated above, the I/O connection boundary registers
12
are so arranged as to be attracted to the cells of the internal logic circuit. Due to this, as shown in
FIG. 1
, the I/O connection boundary scan registers
12
are dispersed on the entire LSI
1
and arranged irrespectively of the flow of test signals. As a result, the nets of test signals to the boundary scan registers cross one another, which disadvantageously causes operation failure due to the backflow or test signals or the like.
Moreover, according to the conventional fan-out adjustment method stated above, since the excessive fan-out is set, excessive buffers are inserted. This disadvantageously causes the increase of the LSI area and the increase of wiring jam.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of designing a layout of an LSI chip capable of automatically arranging boundary scan registers at appropriate positions and capable of making a fan-out adjustment between a test control circuit and the boundary scan registers by inserting a minimum number of buffers. It is another object of this invention to provide a computer readable recording medium that stores a computer program which when executed realizes the method according to the present invention.
The method of designing a layout of an LSI chip according to one aspect of this invention is characterized in that in designing a layout of an LSI chip having boundary scan registers, after arranging I/O cells and before arranging an internal logic circuit and the like, I/O connection boundary scan registers and output I/O control boundary scan registers are preferentially arranged in empty regions near the I/O cells and a fan-out adjustment is made by inserting buffer cells into nets of test signals to the boundary scan registers led to a test control circuit.
According to the above-mentioned aspect of this invention, since the I/O connection boundary scan registers are preferentially arranged after arranging the I/O cells, it is possible to arrange the I/O connection boundary scan registers in the vicinity of the I/O cells along the arrangement of the I/O cells.
In the above-mentioned aspect of this invention, the output I/O control boundary scan registers are arranged at the intermediate points between the I/O connection boundary scan registers, respectively. If the intermediate points are closer to the interior of the chip compared with positions at which the I/O connection boundary scan registers are arranged and have an adverse effect on the arrangement of the internal logic circuit or the like, then the output I/O control boundary scan registers are arranged toward the chip side closer to the intermediate points.
By doing so, the output I/O control boundary scan registers are arranged at the intermediate points between the I/O connection boundary scan registers, respectively. Thus, it is possible to prevent the arrangement of the output I/O control boundary scan registers from being deviated and to regularly arrange the nets between the boundary scan registers in a direction in which test signals flow. Further, if the intermediate points are located closer to the interior of the chip, the output I/O control boundary scan registers are arranged toward the chip side closer to the intermediate points. Thus, it is possible to prevent the boundary scan registers from hampering the arrangement of the internal logic circuit and the like provided in the chip.
Moreover, when making a fan-out adjustment, the wiring length between adjacent boundary scan registers is calculated based on the Manhattan lengths of the boundary scan registers, a wiring capacity is estimated based on the tentative wiring length and buffer cells are inserted into the nets of test signals based on the estimated wiring capacity. In addition, using a coefficient for correcting the difference between the tentative wiring length and an actual wiring length, the driving capabilities of the output terminals of the inserted buffer cells may be corrected. Besides, the positions at which the buffer cells are inserted are in the vicinity of the boundary scan register closest to the test control circuit among a group of boundary scan registers driven by the buffer cells.
By doing so, it is possible to estimate an actual wiring capacity and to determine a position at which the buffer cell is inserted based on the estimated wiring capacity. Due to this, before providing wirings, it is possible to make a fan-out adjustment with a minimum number of buffer cells. In addition, since the fan-out adjustment can be made in a condition far closer to that of actual wirings by using the correction coefficient, it is possible to prevent over-capacity after actually providing wirings more surely. Besides, since the buffer cells are arranged in the vicinity of the boundary scan register arranged closest to the test control circuit, it is possible to prevent timing errors or the like from occurring.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 4967142 (1990-10-01), Sauerwald et al.
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5410491 (1995-04-01), Minami
patent: 5428624 (1995-06-01), Blair et al.
patent: 5477545 (1995-12-01), Huang
patent: 5838580 (1998-11-01), Srivatsa
patent: 6145116 (2000-11-01), Tawada
patent: 6198978 (2001-03-01), Takahashi
patent: 6314547 (2001-11-01), Donath et al.
patent: 6389565 (2002-05-01), Ryan et al.
Abe Koji
Osaki Seiko
Lin Sun James
Siek Vuthe
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