Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-09-19
2003-04-01
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189070
Reexamination Certificate
active
06542422
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a circuit configuration of a redundancy determination circuit for replacing a defective memory cell with a redundant memory cell.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) used as a main memory, though having been progressed in its high speed operation, still cannot follow an operating speed of a microprocessor (MPU). Therefore, a fear exists that an access time and a cycle time of a DRAM act as bottle necks against performance of the system as a whole to reduce it. In recent years, a proposal has been made, in light of such a situation, of a double data rate SDRAM (hereinafter referred to as DDR-SDRAM) operating in synchronization with a complementary clock signal as a main memory for a high speed MPU.
In DDR-SDRAM, for the purpose of a high speed access, specifications are common that get a high speed access to consecutive bits in synchronization with a rise and fall of a clock signal.
A double data rate scheme commonly employs a configuration in which a memory array is divided into two memory blocks: a memory block having even-numbered bit lines corresponding to even-numbered addresses and a memory block having odd-numbered bit lines corresponding to odd-numbered addresses, wherein an even-numbered bit line and an odd-numbered bit line are selected in parallel to each other to get simultaneous accesses, thereby facilitating a data output operation at a double clock frequency. In such a configuration, there has generally been used a method in which an address inputted externally is converted to even-numbered and odd-numbered addresses.
FIG. 7
is a schematic block diagram showing an overall configuration of a conventional synchronous semiconductor memory device
10
.
Referring to
FIG. 7
, a synchronous semiconductor memory device
10
includes: a memory block
6
a
corresponding to even-numbered addresses and a memory block
6
b
corresponding to odd-numbered addresses, which are obtained by dividing a memory array into the two blocks. Memory blocks
6
a
and
6
b
each have memory cells arranged in a matrix and redundant memory cells for saving a defective memory cell. Here, typically shown in memory block
6
a
are one word line WL provided correspondingly to a row, one even-numbered bit line BLE provided correspondingly to a column and one redundant bit line BLSE provided corresponding to a redundant memory cell column constituted of redundant memory cells. In addition, typically shown in memory block
6
b
are one word line WL provided correspondingly to a row, one odd-numbered bit line BLO provided correspondingly to a column and one redundant bit line BLSO provided corresponding to a redundant memory cell column constituted of redundant memory cells. Hereinafter, the redundant bit lines are simply referred to as redundant bit line BLS in a collective manner.
Note that in the following examples, memory blocks
6
a
and
6
b
each have 256 bit lines and a plurality of bit lines, which is one example. Furthermore, in memory block
6
a
, even-numbered addresses are sequentially allocated to even-numbered bit lines. For example, addresses 0#, 2#, 4#, . . . and so on are sequentially allocated. Furthermore, in memory block
6
b
, odd-numbered addresses are sequentially allocated to odd-numbered bit lines. For example, addresses 1#, 3#,5#, . . . and so on are sequentially allocated.
Synchronous semiconductor memory device
10
further includes: a control signal generating circuit
20
generating control signals for internal circuits and control signal generating circuit
20
especially generates an internal clock signal CLK (hereinafter also simply referred to as clock signal CLK) used in timing control of internal circuits in synchronization with an external clock signal Ext.CLK.
Synchronous semiconductor memory device
10
further includes: a now decoder
2
performing row selection in memory blocks
6
a
and
6
b
; column decoders
3
a
and
3
b
receiving, as respective inputs, even-numbered and odd-numbered addresses to perform column selection; spare column decoders
4
a
and
4
b
performing column selection for redundant bit lines BLS in respective memory blocks according to a defect determination signal; a multiplexer
5
a
outputting read data read out from memory block
6
a
to an amplifier
7
a
on the basis of a column select operation by one of column decoder
3
a
and spare column decoder
4
a
; and a multiplexer
5
b
outputting read data read out from memory block
6
b
to an amplifier
7
b
on the basis of a column select operation by one of column decoder
3
b
and a spare column decoder
4
b.
Synchronous semiconductor memory device
10
further includes: amplifiers
7
a
and
7
b
amplifying read data outputted from multiplexers
5
a
and
5
b
; a parallel-serial conversion circuit
8
sequentially arranging two read data amplified by amplifiers
7
a
and
7
b
so as to output the two data in synchronization with a rise and fall, respectively, of clock signal CLK; and an output buffer
9
outputting read data arranged by parallel-serial conversion circuit
8
to an external terminal DQ.
Synchronous semiconductor memory device
10
further includes: a redundancy determination circuit
35
a
for determining redundancy of memory block
6
a
corresponding to an even-numbered address; and a redundancy determination circuit
35
b
for determining redundancy of memory block
6
b
corresponding to an odd-numbered address. Redundancy determination circuits
35
a
and
35
b
include respectively: program circuits
33
a
and
33
b
(hereinafter also referred to as program circuit
33
in a collective manner) setting column addresses of defective memory cells (hereinafter also referred to as defect address); and comparison circuits
32
a
and
32
b
(hereinafter also referred to as comparison circuit
32
in a collective manner) comparing a defective address and an inputted address with each other to generate defect determination signals SCEE and SCEO on the basis of results of the comparisons.
Synchronous semiconductor memory device
10
further includes: an address buffer
30
buffering a column address CA inputted from an external address terminal PINA to output addresses to column decoders
3
a
and
3
b
. Address buffer
30
has a burst counter
31
. Burst counter
31
counts up a bit or bits of part of a column address on the basis of a preset burst length in synchronization with clock signal CLK. Address buffer
30
, on burst reading, latches residual bits obtained after excluding the bit or bits of part of the column address and outputs the residual bits together with the bit or bits of part which have been counted up. Herein, the burst length indicates a length of data outputted consecutively.
Synchronous semiconductor memory device
10
includes an even-numbered address buffer
40
, provided between address buffer
30
and column decoder
3
a
, and generating an even-numbered address CAE for performing a column select operation in memory block
6
a
and even-numbered address buffer
40
receives, as an input, a column address CA including the bit or bits of part, which have been counted up by a burst counter
31
of address buffer
30
. Synchronous semiconductor memory device
10
further includes: an odd-numbered address buffer
50
, provided between address buffer
30
and column decoder
3
b
, and generating an odd-numbered address CAO for performing a column select operation in memory block
6
b
and odd-numbered address buffer
50
receives, as an input, a column address CA including the bit or bits of the part, which have been counted up by burst counter
31
of address buffer
30
.
Address buffer
30
receives column address CA <
8
:
0
> from external address terminal PINA. Note that column address CA <
8
:
0
> is indicated column addresses CA<
0
> to CA<
8
>. Similarly, a symbol <x:
0
> is herei
Furutani Kiyohiro
Hamamoto Takeshi
Kubo Takashi
Lebentritt Michael S.
Nguyen Tuan T.
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