Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-12-17
2003-05-06
Liu, Shuwang (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S374000, C375S375000, C327S147000, C327S148000
Reexamination Certificate
active
06560306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to phase detection circuitry, and, more particularly, to a parallel sampling phase detector with linear output response for use, for example, in data recovery applications.
2. Discussion of the Related Art
There has been much investigation in the area of high bit rate transmitting/receiving circuitry, owing in no small part to the demand for increased bandwidth by the communications industry. In response, organizations such as the IEEE have proposed serial data communications standards with data rates in the Gigabit per second range. To eliminate the need for a separate conductor or optical fiber link carrying a companion clock signal, the above-noted serial communications standards generally call for the timing or clock information to be embedded in the data transmission itself. To insure proper transmission of timing information, it is conventional to require, in the data bitstream, a minimum number of transitions per unit time. To this end, various encoding schemes have been developed (e.g., 8B10B, which defines a 10-bit data word), that transmit a sufficient number of transitions to insure recovery of timing at the far end.
With this background, it has been conventional practice for high speed data recovery systems to use a high frequency voltage-controlled oscillator (VCO) having a frequency substantially equal to the transmission bit rate (line bit rate). Conventional phase detectors, charge pump/loop filters, and VCOs are used to extract the embedded clock from the incoming data stream, and generate a “clean” clock signal operating at the incoming data bit rate. The “clean” clock is used to synchronize the sampling of the incoming data. The sampled data, which is recovered, conventionally, in a serial fashion (i.e., just like the incoming data stream), is then converted using a serial-to-parallel conversion circuit to produce an n-bit data word.
A problem with the foregoing approach, especially as the incoming data bit rate increases into the high frequency (e.g., greater than 1 Gigabit per second range) is that such a system requires a very high frequency VCO (producing a clock signal operating at the line bit rate), and an extremely fast phase detector. This results in relatively high power consumption. In some cases, the called-for bit rate is so high that it may be impractical to generate at all using some (e.g., standard CMOS) semiconductor processes. Moreover, to implement the serial-to-parallel conversion, fast shift registers must be used, which further increase the already relatively high power consumption.
Another approach in the art has been to use a VCO generating multiple phases, each at a frequency lower than the line bit rate, and use these VCO phases with multiple phase detectors. In this approach, fixed pulsewidth “pump up” and “pump down” control pulses are generated which, as is well known, are filtered and used to generate a control signal which varies the output frequency of the VCO. A disadvantage with this approach is that the fixed pulsewidth “pump up” and “pump down” signals result in an increased sensitivity to duty cycle distortion (i.e., a “dead zone” is caused by the fixed pulsewidths which do not provide a linear indication of the phase difference between the VCO clocks and the incoming data stream). In addition, use of the fixed pulsewidth “pump up” and “pump down” signals result in data dependent phase jitter.
Thus, there is a need to provide an improved system for phase detection and/or data recovery that minimizes one or more of the problems as described above.
SUMMARY OF THE INVENTION
The present invention provides a parallel phase detector architecture, and one advantage of that architecture is that a VCO output frequency may be reduced relative to the incoming data bit rate, which in turn reduces the power consumption. For example, according to the invention, a VCO frequency may be f
VCO
=bit rate
, where n is equal to the number of phase detector stages used in the parallel architecture.
Particularly, in one aspect of the present invention, an apparatus for detecting the phase of an input signal relative to an output signal is provided. The apparatus, in one embodiment, includes a plurality of phase detector circuits each coupled to receive the input signal. Importantly, each phase detector provides a phase difference signal proportional to a phase difference between the input signal and the output signal. The apparatus further includes means responsive to the phase difference signal for generating the output signal. In a preferred embodiment, the phase difference signal comprises “pump up” and “pump down” signals wherein one of the pump up signal and the pump down signal, for each phase detector circuit, has a variable pulsewidth to thereby provide a linear response. In the preferred embodiments, the output signal may include a plurality of phases each operating at a frequency lower than the line bit rate of the input signal. This architecture obviates the need for a single, high frequency VCO output signal. A device according to this aspect of the present invention therefore achieves low power consumption. The linear phase detectors substantially minimizes sensitivity to duty cycle distortion as well as data dependent jitter.
In another aspect of the present invention, an improved phase detector is provided which has a linear output. The phase detector may be used during one phase of a multi-phase VCO output signal, such as established by an embodiment according to the first aspect of the invention. In a preferred embodiment, the phase detector includes a D-type memory element, a function gate, and means for generating a pump down signal. The D-type memory element has an input terminal configured to receive an input signal, and an output terminal. The function gate has first and second input terminals, and an output terminal configured to generate a pump up signal. The first and second input terminals of the function gate are connected to the input and output terminals of the D-type memory element. The pulsewidth of, preferably, one of the pump up signal and the pump down signal is proportional to a phase difference between the input signal, which may be an incoming data signal, and the output signal, which may be generated from a multi-phase VCO. The pump down signal generating means is responsive to at least one of the pump up signal and the memory element output signal to generate the pump down signal.
Other objects, features and advantages of the present invention will become apparent to one skilled in the art from the following detailed description and accompanying drawings illustrating features of this invention by way of example, but not by way of limitation.
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Duffy Michael L.
Navabi Mohammad J.
Cypress Semiconductor Corp.
Liu Shuwang
Maiorana P.C. Christopher P.
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