Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-13
2002-10-08
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000
Reexamination Certificate
active
06462371
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.
BACKGROUND OF THE INVENTION
Modern semiconductor device fabrication processes frequently use selective etching conditions that will etch one material more rapidly than another. The material that is etched more rapidly can be referred to as a sacrificial material, and the material that is etched less rapidly can be referred to as a protective or etch stop material. Selective etching can be use in processes in which it is desired to protect a portion of a semiconductor wafer from etching conditions while etching through another portion of the wafer. Exemplary selective etching conditions are dry etch conditions that are selective for etching silicon oxide relative to silicon nitride, including those described in U.S. Pat. No. 5,286,344, the disclosure of which is incorporated by reference herein in its entirety.
Many prior art selective etching methods generally have poor selectivities, such that there is a constant risk that the protective material will be etched away entirely during the etching of the sacrificial material. The selectivity for a given selective etching method is highly dependent on numerous factors, such as the composition of the film and the etching conditions. It would be desirable to develop alternative methods of selective etching having better selectivities under comparable conditions.
A possible mechanism by which selectivity can occur is through selective polymer formation on the protective material during etching of it and the sacrificial material. For instance, etching of silicon oxide and silicon nitride under conditions such as those described in U.S. Pat. No. 5,286,344 can create a carbonaceous polymer on the silicon nitride which protects the silicon nitride during etching of the silicon oxide. The carbon contained in the carbonaceous polymer can originate from, for example, etchant materials, such as gas, liquid or plasma materials, including, for example, CH
2
F
2
and CHF
3
. When silicon oxide, such as borophosphosilicate glass (also referred to throughout the specification as BPSG), is selectively etched relative to silicon nitride, the carbon will frequently originate at least in part from etching of the BPSG. Thus, less selectivity is obtained when less BPSG is etched relative to an amount of silicon nitride exposed to the etching conditions. Accordingly, thin layers of BPSG can be more difficult to etch than thick layers. Many selective etching methods are not effective for selectively etching BPSG relative to silicon nitride when the BPSG layers have thicknesses of less than or equal to about 1.3 microns.
An exemplary application of selective etching is a dynamic random access memory (DRAM) forming process. Referring to
FIG. 1
, a DRAM construction is illustrated with respect to semiconductive wafer fragment
10
. Semiconductive wafer fragment
10
comprises a substrate
12
, which can be, for example, a monocrystalline wafer lightly doped with a p-type background dopant. The term “semiconductive wafer fragment” refers to any construction comprising semiconductive materials, including, for example, bulk semiconductive materials, such as semiconductive wafers (either alone or in assemblies comprising other materials thereon) and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, for example, the semiconductive wafer fragments described above.
Field oxide regions
15
overlay the substrate
12
, and node locations
14
,
16
are between the field oxide regions
15
. The node locations
14
,
16
contain diffusion regions conductively doped with a conductivity-enhancing dopant.
Wordlines
20
overlay the substrate
12
. The wordlines
20
comprise a gate oxide layer
24
and a conductive layer
26
. The gate oxide layer
24
and conductive layer
26
may also be referred to as a conductive gate. The gate oxide layer
24
can comprise, for example, silicon dioxide. The conductive layer
26
can comprise, for example, conductively doped polysilicon capped with a metal silicide, such as, for example, tungsten silicide or titanium silicide. The wordlines
20
have opposing sidewall edges and sidewall spacers
28
(referred to herein as a “spacer” or “spacers”) that extend along the sidewall edges. The spacers
28
can comprise, for example, silicon oxide or silicon nitride. An etch stop layer
32
extends over the wordlines
20
. The etch stop layer
32
can comprise, for example, silicon nitride. Although not shown, an insulative layer can be placed between the etch stop layer
32
and the conductive layer
26
. The insulative layer can comprise, for example, silicon oxide or silicon nitride.
An insulative layer
34
is provided over the substrate
12
and over the wordlines
20
. The insulative layer
34
can comprise, for example, BPSG.
Capacitor constructions
36
extend through the insulative layer
34
to contact the node locations
14
. The capacitor constructions
36
comprise a storage node or first electrode
40
, a dielectric layer
42
, and a second electrode
44
. The storage node
40
and second electrode
44
can comprise, for example, conductively doped silicon such as a conductively doped polysilicon. The dielectric layer
42
can comprise, for example, silicon dioxide and/or silicon nitride. Although all the layers
40
,
42
,
44
are shown extending within openings in the insulative layer
34
, other capacitor constructions can be used where some or none of the storage node, dielectric and second electrode layers extend within the opening.
A bit line contact
46
also extends through the insulative layer
34
and contacts a node location
16
. The bit line contact
46
is in gated electrical connection with the capacitor construction
36
through the wordline
20
. The bit line contact
46
can comprise, for example, tungsten, titanium and/or titanium nitride. Although not shown, a diffusion barrier layer, such as, for example, titanium nitride, can be formed between the bit line contact
46
and the diffusion region of the node location
16
.
A second insulative layer
48
extends over the capacitor constructions
36
and electrically isolates the second electrode
44
from the bit line contact
46
. The second insulative layer
48
can comprise, for example, silicon dioxide, BPSG or silicon nitride, and can be the same as or different from the first insulative layer
34
.
A bit line
50
extends over the second insulative layer
48
and is in electrical connection with the bit line contact
46
. Accordingly, the bit line contact
46
electrically connects the bit line
50
to the node location
16
. The bit line
50
can comprise, for example, aluminum, copper or an alloy of aluminum and copper.
A method of forming the DRAM construction of
FIG. 1
is described with reference to
FIGS. 2 and 3
.
FIG. 2
illustrates a semiconductive wafer fragment
10
at a preliminary processing step. The etch stop layer
32
extends over the wordlines
20
, and over the node locations
14
,
16
. The insulative layer
34
extends over the etch stop layer
32
, and a patterned photoresist masking layer
60
is provided over the insulative layer
34
. The patterned photoresist masking layer
60
defines an opening
62
which is to be extended to the node location
16
for ultimate formation of the bit line contact
46
therein.
Referring to
FIG. 3
, the opening
62
is extended to the etch stop layer
32
. The etch used to extend the opening
62
is preferably selective for the material of the insulative layer
34
relative to that of the etch stop layer
32
. For instance, if the insulative layer
34
comprises BPSG and the etch stop layer
32
comprises nitride, the et
Moore John T.
Weimer Ronald A.
Hale and Dorr LLP
Loke Steven
Micro)n Technology, Inc.
Nguyen Cuong Quang
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