Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-07-25
2002-10-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S197000, C438S299000, C438S303000, C438S592000, C438S682000
Reexamination Certificate
active
06458678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor processing and, more particularly, to a transistor formed using a dual metal process for gate and source/drain region.
2. Description of the Related Art
Semiconductor integrated circuit devices are employed in numerous applications, including microprocessors. Generally, the performance of a semiconductor device is dependent on both the density and the speed of the devices formed therein. A common element of a semiconductor device that has a great impact on its performance is a transistor. Design features, such as gate length and channel length, are being steadily decreased in order to achieve higher package densities and to improve device performance. The rapid advance of field effect transistor design has affected a large variety of activities in the field of electronics in which the transistors are operated in a binary switching mode. In particular, complex digital circuits, such as microprocessors and the like, demand fast-switching transistors. Accordingly, the distance between the drain region and the source region of a field effect transistor, commonly referred to as the channel length or gate length dimension, has been reduced to accelerate the formation of a conductive channel between a source and a drain electrode as soon as a switching gate voltage is applied and, moreover, to reduce the electrical resistance of the channel.
A transistor structure has been created where the longitudinal dimension of the transistor, commonly referred to as the width dimension, extends up to 20 &mgr;m, whereas the distance of the drain and source, i.e., the gate length, may be reduced down to 0.2 &mgr;m or less. As the gate length of the channel has been reduced to obtain the desired switching characteristic of the source-drain line, the length of the gate electrode is also reduced. Since the gate electrode is typically contacted at one end of its structure, the electrical charges have to be transported along the entire width of the gate electrode, i.e., up to 20 &mgr;m, to uniformly build up the transverse electric field that is necessary for forming the channel between the source and drain regions. Due to the small length of the gate electrode, which usually consists of polycrystalline silicon, the electrical resistance of the gate electrode is relatively high, and it may cause high RC-delay time constants. Hence, the transverse electrical field necessary for fully opening the channel is delayed, thereby further deteriorating the switching time of the transistor line. As a consequence, the rise and fall times of the electrical signals are increased, and the operating frequency, i.e., the clock frequency, has to be selected so as to take into account the aforementioned signal performance.
In view of the foregoing, the switching times of field effect transistors are no longer only limited by the drain and source characteristics, i.e., dimension and resistance, but also significantly depend on the signal propagation along the gate electrode. However, the resistance of the gate electrode affects the propagation time of a signal along the gate width direction. To minimize the electrical resistance of the drain and source regions, as well as that of the gate electrode, a silicidation process is usually performed in which a portion of the aforementioned regions are transformed into a metal silicide region in order to lower the respective electrical resistances. The depth of the metal silicide regions on the surfaces of the drain region, source region and gate electrode is limited by the requirements for the integrity of shallow drain/source junctions. That is, the metal silicide regions can only be made a certain thickness without adversely impacting the source/drain regions.
Transistors are formed through a series of steps. First, a gate insulation layer is formed over a portion of a substrate. Thereafter, a polysilicon gate electrode is formed over the gate insulation layer. Implants are then conducted to form source/drain (S/D) regions of the transistor. Typically, a metal silicide layer, such as titanium silicide is formed over the source/drain regions and a top portion of the gate electrode to lower the resistance of subsequently formed contacts. Reductions in contact resistance to the various parts of the transistor increases the speed of the device by reducing the time constants associated with its operation.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for forming a semiconductor device. The method includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, and a first metal silicide layer is formed over the source drain regions. The thickness of the gate electrode is reduced, and a second metal silicide layer is formed over the reduced thickness gate electrode.
REFERENCES:
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5656519 (1997-08-01), Mogami
patent: 5731239 (1998-03-01), Wong et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 5966597 (1999-10-01), Wright
patent: 5994193 (1999-11-01), Gardner et al.
Hause Frederick N.
Spikes, Jr. Thomas E.
Wu David D.
Lytle Craig P.
Smith Matthew
Williams Morgan & Amerson P.C.
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