Plated through hole interconnections

Details Plated through hole interconnections Plated through hole interconnections

2001-04-11

2002-10-01

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S667000, C205S131000, C205S151000, C205S157000

Reexamination Certificate

active

06458696

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic assembly technology and more specifically to interconnections on semiconductor wafers.
BACKGROUND OF THE INVENTION
A sophisticated and widely used interconnection technology has been developed for connecting one electrical site on a semiconductor wafer to another. Typically these interconnections involve connecting the active elements of a semiconductor device, e.g. source, drain, gate, to each other, or to another device, or to a runner that interconnects to another level. In early device technology, and in some simple large area devices in current production, these interconnections are made on a single level on the surface of the semiconductor wafer. As device dimensions have been reduced, and the complexity of interconnections increased, multiple level interconnections were developed. These are stacked on the semiconductor wafer surface over the active devices. Three or even four levels of interconnection are not uncommon.
Recently, new technologies have arisen where one or more interconnect levels are formed directly on the semiconductor surface, and the active device is located above the interconnect levels. However, in both of these cases all of the device structure, including the interconnections, are located on the same side of the wafer.
New photonic devices are in development that use micromechanical elements. In principle micromechanical elements can be built on a variety of platforms, not necessarily semiconductor platforms. However, highly and often elegantly engineered silicon processing can be used to make new device structures that combine mainly the mechanical and optical properties of silicon. Consequently, so-called silicon optical bench technology has evolved in which the platform for the micromechanical devices or subassemblies is a silicon wafer, or a large silicon chip.
Among the most promising of the photonic micromechanical devices are optical switches. These devices typically comprise mirrors, and the mirrors operate as moving parts. The movement of the mirrors in these devices may be effected by magnetic or electric fields, both activated using electrical circuitry. To date, the electrical circuits have been built around the micromechanical elements to interconnect them together. As the size of the micromechanical arrays, and the number of devices per wafer, increases, the electrical circuits that drive them become more complex. The usual option when confronted with increased complexity is to build interconnect layers on top of the active structures, as in state of the art IC technology. However, with micromechanical mirror arrays, this option is limited by both the need for movement of the micromechanical elements and the need for accessing these elements, e.g., mirrors, with optical beams. The solution to interconnect congestion in large micro-mirror arrays to date has been to increase the platform area.
To overcome this serious limitation an interconnect technology for micromechanical devices has been developed in which the micromechanical elements are located on the top side of the silicon wafer platform but most of the interconnection for the electrical circuits that drive the micromechanical elements is located on the backside, i.e. bottom side, of the silicon wafer. For more details of this technology, see U.S. application Ser. No. 09/578,894, filed May 26, 2000, which application is incorporated herein in its entirety for relevant details.
The interconnect strategy of the aforementioned application leads to several important advantages. It provides more area for interconnections. It allows effective use of multilevel interconnect layers. It provides space, with concomitant short interconnections, for attachment of active drive IC devices. It removes a source of stray electromagnetic fields from the top surface, where the electrostatic drive elements for mirror tilt are susceptible to unwanted interactions, to the bottom surface remote from the mirror tilt apparatus. An important aspect of this new technology is that the interconnections are made using through holes that extend from the front side of the silicon wafer to the backside through the thickness of the silicon wafer. However, a contradiction in design is raised by three considerations: 1. the silicon wafer should be relatively thick to have sufficient mechanical robustness for handling and supporting the mechanical apparatus; 2. the through holes should have as small a diameter as possible to allow optimum miniaturization of the micromechanical elements and the interconnections for those elements; 3. the through holes need to be large enough to accommodate both an insulating layer and a conductor plug, and also need to be large enough to allow for processing through the entire thickness of the wafer in forming the insulating layer and the conductive plug. The latter problem will be appreciated from the fact that the two former requirements result in hole aspect ratios typically greater than 4, which is widely regarded by workers in the art as a severe constraint on process design choice. The usual wafer thickness for micromechanical device platforms is at least 500 &mgr;m, and the through hole diameter requirement is less than 125 &mgr;m. Both the relative dimensions quoted, i.e. the aspect ratio, and the absolute dimensions, are important. As the (absolute) diameter is reduced below 125 &mgr;m the options for processing high aspect ratio holes become limited. One useful option is described in the application referenced above. It is to coat the walls of the through hole with thermally grown oxide, and fill the coated holes with CVD polysilicon. Both of these are vapor phase processes, which are expected to be the choice of the process designer in view of the limitations due to the high aspect ratio of the through holes. The choice of polysilicon as the fill material is advantageous for thermo-mechanical integrity of the wafer. However, it is known that the deposition of very thick films of heavily doped polysilicon is a slow process. Moreover, the conductivity of polysilicon, while acceptable, is not ideal. It would be desirable to fill the through holes with a more conductive interconnection material.
SUMMARY OF THE INVENTION
It has been discovered, unexpectedly, that an electrolytic process is effective for coating the entire surface of through holes having very small diameters, e.g. 20 to 150 &mgr;m, and very high aspect ratios, e.g. greater than 4. This allows electroplating of high aspect through holes with copper or nickel.


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