Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-13
2002-10-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06470479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of verifying semiconductor integrated circuit reliability, especially, a method of verifying the reliability of interconnect lines in a semiconductor integrated circuit.
2. Description of the Background Art
One of the factors that impair the reliability of metallic interconnect lines in a semiconductor integrated circuit is electromigration. To ensure the reliability of a semiconductor integrated circuit, an electromigration failure rate must be suppressed below a predetermined level, and whether the failure rate is not more than a guaranteed failure rate must be verified at the design stage.
As a conventional way to detect metallic interconnect lines having a high electromigration failure rate in a semiconductor integrated circuit, there is a method using circuit simulations. For example, a circuit simulator called “SPICE (Simulation Program with Integrated Circuit Emphasis) is used to calculate current waveforms flowing in interconnect lines connected to each node.
Concurrently with this, layout data for the interconnect lines connected to each node is extracted from a circuit layout, and accelerated life evaluation data is obtained using an interconnection test structure. On the basis of the current waveforms from the SPICE simulator, the layout data, and the accelerated evaluation data, the failure rate of each metallic interconnect line due to electromigration is calculated. When the resultant failure rate is more than a reference value, the metallic interconnect line is extracted as having a high failure rate.
This method, however, takes much time to extract layout data for a complex interconnect line and is thus not applicable for a large-scale semiconductor integrated circuit. Further, large-scale circuits require enormous amounts of time for circuit simulations and a mass storage device to store waveform data for each node. This increases the difficulty of applying this method to a large-scale semiconductor integrated circuit.
In addition, input waveforms of circuit simulators such as SPICE cannot cover all circuits, which carries a risk that some non-operating circuits may be left unverified.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a method of verifying the reliability of a semiconductor integrated circuit using a cell library database. The semiconductor device includes a plurality of cells connected with each other by at least one intercellular interconnect line. The cell library database contains inner-cell input/output load capacity information including input load capacity and output load capacity of each of the plurality of cells, and information about a way to calculate a failure rate of an inner-cell interconnect line based on load capacity on an external terminal of each of the plurality of cells. The method comprises the steps of: (a) obtaining load capacity on the external terminal on the basis of the inner-cell input/output load capacity information; and (b) calculating a failure rate of an inner-cell interconnect line in a cell which has the external terminal, on the basis of the load capacity on the external terminal according to the way to calculate a failure rate, the steps (a) and (b) being performed for each of the plurality of cells.
According to a second aspect of the present invention, in the method of the first aspect, the step (a) includes the steps of: (a-1) obtaining a sum total of inner-cell input/output load capacities on the external terminal on the basis of the inner-cell input/output load capacity information; (a-2) obtaining wiring capacitance of an intercellular interconnect line which is connected to the external terminal, according to an equation of an intercellular interconnect line with the sum total of inner-cell input/output load capacities as a parameter; and (a-3) obtaining the load capacity on the external terminal by adding the wiring capacitance to the sum total of inner-cell input/output load capacities.
According to a third aspect of the present invention, in the method of the first aspect, the step (a) includes the steps of: (a-1) obtaining a sum total of inner-cell input/output load capacities on the external terminal on the basis of the inner-cell input/output load capacity information; (a-2) obtaining wiring capacitance of an intercellular interconnect line which is connected to the external terminal, on the basis of layout information about the intercellular interconnect line; and (a-3) obtaining the load capacity on the external terminal by adding the wiring capacitance to the sum total of inner-cell input/output load capacities.
According to a fourth aspect of the present invention, in the method of the third aspect, the intercellular interconnect line includes a plurality of intercellular interconnect elements which are connected with each other through via holes and which can be recognized from the layout information about the intercellular interconnect line. The method further comprises the steps of: (c) obtaining a failure rate of each intercellular interconnect element which is longer than a predetermined critical length out of the plurality of intercellular interconnect elements on the basis of the load capacity on the external terminal, and adding up the obtained failure rate of each intercellular interconnect element to obtain a failure rate of the intercellular interconnect line; and (d) obtaining a total failure rate by adding the failure rate of the intercellular interconnect line to the failure rate of the inner-cell interconnect line, the steps (c) and (d) being performed for each of the plurality of cells.
According to a fifth aspect of the present invention, the method of either of the first through third aspects further comprises the steps of: (c) obtaining a failure rate of the intercellular interconnect line on the basis of the load capacity on the external terminal; and (d) obtaining a total failure rate by adding the failure rate of the intercellular interconnect line to the failure rate of the inner-cell interconnect line, the steps (c) and (b) being performed for each of the plurality of cells.
According to a sixth aspect of the present invention, in the method of the fifth aspect, the cell library database further contains directional information indicating whether the external terminal of each of the plurality of cells is a bidirectional terminal that can be both charged and discharged or an unidirectional terminal that can be either charged or discharged, and the step (c) includes the steps of: (c-1) determining whether the external terminal is the bidirectional terminal or the unidirectional terminal on the basis of the directional information; (c-2) when the external terminal is the bidirectional terminal, calculating a failure rate of the intercellular interconnect line according to a first way; and (c-3) when the external terminal is the unidirectional terminal, calculating a failure rate of the intercellular interconnect line according to a second way different from the first way.
According to a seventh aspect of the present invention, the method of either of the first through sixth aspects further comprises the steps of: (e) after the step (a), calculating a mean current value flowing in the intercellular interconnect line on the basis of the load capacity on the external terminal and, when the mean current value is not more than a preset current value, forcefully skipping the calculation of a failure rate of a cell having the external terminal, the step (e) being performed for each of the plurality of cells.
According to an eighth aspect of the present invention, in the method of either of the first through seventh aspects, the cell library database further contains operating-ratio information indicating an operating ratio which is the number of operations of each of the plurality of cells during a predetermined period of time, and the step (b) includes the step of calculating a failure rate of the inner-cell interconnect line in consideration of the
Levin Naum
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
LandOfFree
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