Method of fabrication of a contact plug in an embedded memory

Details Method of fabrication of a contact plug in an embedded memory Method of fabrication of a contact plug in an embedded memory

2001-06-21

2002-10-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S241000, C438S396000

Reexamination Certificate

active

06461959

ABSTRACT:

FIELD OF THE INVENTION
The present invention provides a method for fabrication of a contact plug in an embedded memory, and, more specifically, to a contact plug with reduced resistance.
DESCRIPTION OF THE PRIOR ART
In order to avoid short-circuiting of devices in an embedded memory, an insulation layer is positioned between each device and the circuit as a whole. A photo-etching process (PEP) is then used to form a plurality of contact holes in the insulation layer. A conductive layer fills each contact hole to electrically connect each metal-oxide-semiconductor (MOS) transistor with the circuit.
Please refer to
FIG. 1
to FIG.
8
.
FIG. 1
to
FIG. 8
are schematic diagrams of a method of fabricating a landing via and a strip contact in an embedded memory according to the prior art. As shown in
FIG. 1
, defined on the surface of a silicon substrate
16
of a semiconductor wafer
10
is a memory array region
12
and a periphery circuit region
14
. The memory array region
12
comprises at least a cell-well
18
, and the periphery circuit region
14
comprises at least an N-well
20
and a P-well
22
. In the prior art, a plurality of gates
24
,
26
,
28
are first formed, separately, in the memory array region
12
and in the periphery circuit region
14
. A spacer
30
and a lightly doped drain (LDD)
32
are formed adjacent to each gate
24
,
26
,
28
. As well, a source
34
and a drain
36
are also formed adjacent the gates
26
,
28
, which are isolated from each other by the shallow trench isolation (STI) structure
15
.
As shown in
FIG. 2
, a dielectric layer
38
, such as a silicon oxide layer, is then formed on the surface of the semiconductor wafer
10
. A photo lithographic process is used to define a pattern of several shallow metal connection regions
40
on the surface of the dielectric layer
38
, as shown in FIG.
3
. Next, another photolithographic process is performed to define a first contact window
44
, a second contact window
42
, and a third contact window
46
in the dielectric layer
38
, as shown in FIG.
4
. The first contact window
44
is used to connect to a capacitor, the second contact window
42
subsequently forms a landing via and connects to a bit line, and the third contact window
46
subsequently forms a strip contact and connects to a source or drain in the periphery circuit region
14
. The depths of the first contact window
44
, the second contact window
42
and the third contact window
46
are all equal, and thus the three contact windows are horizontally aligned.
As shown in
FIG. 5
, a photolithographic process is then used to form a fourth contact window
48
in the dielectric layer
38
. The fourth contact window
48
is used to connect to a gate in the strip contact of the periphery circuit region
14
. Since the depth of the fourth contact window
48
is shallower than that of the other contact windows, its horizontal alignment differs to that of the first contact window
44
, the second contact window
42
and the third contact window
46
. The third contact window
46
and the fourth contact window
48
are separately connected to the gate and source or drain of transistors, and therefore the two contact windows are located on different vertical planes. As shown in
FIG. 6
, a barrier layer
50
of titanium nitride and a dielectric layer
52
of tantalum oxide are formed, respectively, on the substrate
16
.
As shown in
FIG. 7
, a photoresist layer (not shown) is used as a mask to etch the dielectric layer
52
so that the dielectric layer
52
remains only in the second contact window
42
and its associated metal connection region
40
. As shown in
FIG. 8
, a metal layer
54
is deposited on the surface of substrate
16
that fills each contact window
42
,
44
,
46
,
48
, and each metal connection region
40
. Finally, the dielectric layer
38
is used as an etching stop layer for chemical mechanical polishing (CMP) of the metal layer
54
.
However, in the disclosure of the prior art method for fabricating an embedded memory, the landing via and local interconnect are separately formed after fabricating each gate in memory array region and the periphery circuit region. The process according to prior art is thus more complicated and costly. Moreover, only a conductive layer fills each landing via and local interconnect to serve as a conducting material, leading to higher contact resistance and poor electrical conductance.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a fabrication method of a contact plug in an embedded memory, integrating the fabrication process of each gate and contact plug, and to reduce the resistance of each contact plug.
The present method involves first forming a first dielectric layer and an undoped polysilicon layer on the surface of a semiconductor wafer that has both a memory array region and a periphery circuit region. The undoped polysilicon layer in the memory array region is then transformed to a doped polysilicon layer, followed by forming a passivation layer and a first photoresist layer on the surface of the semiconductor wafer to form a plurality of gates and LDDs in the memory array region. Next, a silicon nitride layer, a second dielectric layer, and a second photoresist layer are formed on the surface of the semiconductor wafer. A plurality of contact plug holes are then formed in the second dielectric layer and filled by a polysilicon layer to form each contact plug in the memory array region. The second dielectric layer, the silicon nitride layer and the passivation layer in the periphery circuit region are removed to form each gate in the periphery circuit region. Thereafter, LDDs and spacers are formed for each gate in the periphery circuit region, followed by forming a source and drain adjacent to each gate in the periphery circuit region. Finally, a self-aligned silicide (salicide) process is performed to form a silicide layer on the top surface of each contact plug in the memory array region, on the top surface of each gate and the surface of each source and drain in the periphery circuit region. The silicide layer formed on the surface of each contact plug is used to reduce the contact resistance of each contact plug.
The present method of fabricating contact plugs in an embedded memory integrates the fabrication process of each gate and contact plug in the memory array region and periphery circuit region of the embedded memory. Also, the present invention simultaneously forms a silicide layer on the top surface of each contact plug in the memory array region, on the top surface of each gate and the surface of each source and drain in the periphery circuit region. As a result, electrical resistance is decreased and electrical performance is increased.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 6168985 (2001-01-01), Asano

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