Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-14
2002-12-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C250S492200, C257S048000, C257S208000, C324S762010, C438S009000, C438S291000, C438S640000
Reexamination Certificate
active
06496959
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and a system for estimating a plasma damage to a semiconductor device, for example, a gate insulation film, for a layout design of the semiconductor device, and more particularly to a storage medium storing a support program for the layout design.
Semiconductor devices such as microprocessors and semiconductor memories have various active and passive devices and interconnection inter-connecting them which are integrated over a single crystal semiconductor substrate such as a silicon substrate. MOS field effect transistors are often utilized as active devices as being advantageous in realizing the required high integration. The MOS field effect transistor has the following essential structural elements. Source and drain regions are selectively formed in the semiconductor substrate by selective ion-implantation of n-type impurity such as arsenic or p-type impurity such as boron. A channel region is defined between the source and drain regions. A gate insulation film such as silicon dioxide film is formed on the channel region. A gate electrode such as a polysilicon gate electrode is formed on the gate insulation film.
In the manufacturing processes for the semiconductor devices, a dry etching process using a plasma is carried out. For example, the interconnections are formed as follows. An interconnection material such as aluminum is entirely deposited over the semiconductor substrate on which transistors have already been formed. A resist is applied on the interconnection material. An exposure and a development to the resist are then carried out to form a resist pattern on the interconnection material. A plasma etching to the interconnection material is carried out by use of the resist pattern as a mask, thereby forming an interconnection. This plasma etching is advantageous in high etching selectively. This plasma etching is superior for realizing shrinkage of the semiconductor device and increasing the degree of integration of the semiconductor devices.
As the MOS field effect transistor is scaled down, the thickness of the gate insulation film is reduced. It will be considered that an aluminum interconnection is formed which is connected to the gate. Charge of the charge particles of the plasma is supplied through the interconnection to the gate. As a result, a current flows through the gate insulation film, whereby the gate insulation film receives a substantive damage upon the current. Thus causes a drop of yield of the semiconductor device and also a drop in reliability of the semiconductor device. The damage that the gate insulation film receives in the process using the plasma is so called as a plasma damage. The degree of the plasma damage depends upon a size of the interconnection being exposed to the plasma and capturing the charges of the charge particles of the plasma.
FIG. 1
is a fragmentary schematic perspective view illustrative of a semiconductor device to explain a mechanism of causing the plasma damage to the gate insulation film. Field oxide films
3
are selectively formed on a surface of a semiconductor substrate
1
so that an active region
2
is defined by the field oxide film
3
. A gate oxide film
4
is formed on the active region
2
of the semiconductor substrate
1
. A gate electrode
5
is formed, which extends over the gate oxide film
4
and parts of the field oxide films
3
. An inter-layer insulator
6
is entirely formed over the gate electrode
5
and the field oxide film
3
. A through hole
7
is formed in the inter-layer insulator
6
and over the gate electrode
5
, so that the through hole
7
reaches a part of the top surface of the gate electrode
5
.
An aluminum layer is entirely deposited over the inter-layer insulator and also within the through hole
7
, so that the aluminum layer within the through hole
7
is in contact with the part of the top surface of the gate electrode
5
. A resist is entirely applied on the aluminum layer and then baked. The resist is patterned by a lithography technique to form a resist pattern
9
on the aluminum layer. A plasma etching to the aluminum layer is then carried out by use of the resist pattern
9
as a mask to form an aluminum interconnection
8
.
The resist pattern
9
exists over the aluminum interconnection
8
. A top surface of the aluminum interconnection
8
is covered by the resist pattern
9
and separated from the plasma, whilst side portions of the aluminum interconnection
8
are exposed to the plasma. Charges of the charge particles of the plasma are captured through the side portions of the aluminum interconnection
8
. Namely, the side portions of the aluminum interconnection
8
serve as antenna for capturing the charges of the charge particles of the plasma. The captured charges are supplied through the through hole
7
to the gate electrode
5
, whereby the gate electrode
5
is positively charged. As the gate electrode
5
is charged, then a current flows through the gate oxide film
4
, whereby the gate oxide film
4
receives the plasma damage. As an area of side walls or side portions of the aluminum interconnection
8
is increased, then the degree of the plasma damage to the gate oxide film
4
is also increased. In general, the degree of the plasma damage to the gate oxide film
4
is approximately proportional to a density of the current.
If the thickens of the aluminum interconnection
8
is fixed, then the amount of the current flowing through the gate oxide film
4
is almost proportional to a length of the circumference of the aluminum interconnection
8
, whilst the amount of the current flowing through the gate oxide film
4
is almost inversely proportional to the area of the gate oxide film
4
. In prior art, the following antenna ratio “R” is used as an index which represents the degree of the plasma damage.
“R”=M/S
where M is the length of the circumference of the aluminum interconnection
8
, and S is the area of the gate oxide film
4
. The length of the circumference of the aluminum interconnection
8
is almost equal to double of the length of the aluminum interconnection
8
.
In consideration of the plasma damage to the gate oxide film
4
due to the charge particles of the plasma, a maximum antenna ratio “Rmax” is previously determined as a design rule, wherein the maximum antenna ratio “Rmax” corresponds to the highest value of acceptable range of the degree of the plasma damage to the gate oxide film. The layout design for the semiconductor device is carried out so that the antenna ratio “R” is not more than the maximum antenna ratio “Rmax”.
It is assumed that the interconnection comprises laminations of three layers, for example, a first metal layer M
1
, a second metal layer M
2
, and a third metal layer M
3
. If the plasma etching process is carried out to form each of the first, second, and third metal layers of the interconnection, then the antenna ratio “R” of the interconnection corresponds to the sum &Sgr;R of individual antenna ratios of the first, second, and third metal layers of the interconnection. In this case, the layout design for the interconnection is carried out so that the sum &Sgr;R of individual antenna ratios of the first, second, and third metal layers is not more than the maximum antenna ratio “Rmax”.
If the interconnection layer comprises laminations of plural layers, then a contact within the contact hole also comprises the laminations of plural layers. The layout design is carried out so that the total sum of the individual antenna ratios of the plural layers does not exceed the maximum antenna ratio “Rmax”. The bottom of the contact within the through hole serves as an antenna. The amount of the current flowing through the gate oxide film
4
is almost proportional to the area of the bottom of the through hole
7
and also almost inversely proportional to the area of the gate oxide film
4
. The area of the bottom of the through hole
7
corresponds to the antenna size M so that the antenna ratio “R” is calculated.
The above conventional te
Liu Andrea
NEC Corporation
Siek Vuthe
Young & Thompson
LandOfFree
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