Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-10-31
2002-12-24
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S342000, C257S339000, C257S763000, C257S766000
Reexamination Certificate
active
06498366
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device which has a low ON-resistance, and further, to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Many kinds of methods of manufacturing for reducing an ON-resistance of a semiconductor device have been known. For example, Japanese Unexamined Patent Publication 1-169970 discloses a method which an N-type impurity layer is formed in a back surface of a drain substrate so as to reduce a contact resistance between the drain substrate and a drain electrode. Japanese Examined Patent Publication 58-45814 discloses a method of manufacturing the semiconductor device which has a good ohmic contact between the drain substrate and the drain electrode. The device has a multilayer metal electrode on a back surface of a drain substrate. The multilayer metal electrode consists of layers having a gold layer as a main layer.
As shown in
FIG. 13
, the ON-resistance of a field effect transistor (FET) is represented by the following equation:
R
ON
=R
1
+
R
2
+
R
3
+
R
4
+
R
5
+
R
6
+
R
7
+
R
8
+
R
9
+
R
10
wherein, R
1
denotes a contact resistance of a drain electrode
50
; R
2
denotes a contact resistance between the drain electrode
50
and an N-Type impurity layer
52
; R
3
denotes a resistance of N drain substrate
54
; R
4
, R
5
and R
6
denote resistances of N drain region
56
respectively; R
7
denotes a resistance of P-Type diffusion region
58
for forming a channel; R
8
denotes a resistance of N-type source
60
; R
9
denotes a contact resistance between the N-Type source
60
and a source electrode
62
; and R
10
denotes a resistance of the source electrode
62
.
However, such a conventional method of manufacturing the semiconductor device has many problems. For example, the method by which the N-Type impurity layer is formed is complex because an oxide film adhered to the back surface of the N drain substrate
54
and a diffusion layer having an opposite conductive type (P) to that of the N drain substrate
54
must be removed before the N-type impurity layer
52
is formed.
A semiconductor device for household use is demanded with a withstanding voltage more than 100V, normally more than 200V. It is a necessary to make a resistance of a epitaxial layer (the N drain region
56
) formed on the N drain substrate
54
high to get the withstanding voltage. Therefore, the ratio of the resistance of the N drain substrate
54
to the resistance of the epitaxial layer becomes small. On the contrary, a semiconductor device for a motor vehicle is demanded with a withstanding voltage of at most 50-60V. The resistance of the epitaxial layer is relatively low, and the ratio of the resistance of N drain substrate
54
to the resistance of the epitaxial layer becomes large. Therefore, in the semiconductor device for a motor vehicle, it is effective to reduce the resistance of the N drain substrate
54
for reducing the ON-resistance.
The resistance R
3
of the N drain substrate
54
is represented by the following equation:
R
3
=&rgr;
N
×t
n
/S
wherein, &rgr;
N
denotes resistivity of the N drain substrate
54
; t
n
denotes a thickness of the N drain substrate
54
; and S denotes a cross section of the N drain substrate
54
. It is necessary to reduce the thickness t
n
of the N drain substrate
54
so as to reduce this resistance R
3
. However, the thickness t
n
of the N drain substrate
54
for forming the N-Type impurity layer
52
is determined in accordance with a thickness of a silicon wafer. The reason is that the N drain substrate
54
is warped by heat generated in a step that the N-Type impurity layer
52
is formed when the thickness t
n
of the N drain substrate
54
is too thin. To get a wafer of large diameter, the thickness t
n
needs to be thick to keep the strength thereof. Therefore, the resistance R
3
of the N drain substrate
54
becomes high, and thus the ON-resistance also becomes high.
The technique by which the concentration of antimony (Sb) as a impurity in the N drain substrate
54
is heightened and the resistivity is diminished, may be adopted so as to reduce the resistance R
3
of the N drain substrate
54
. However, it is impossible to make the resistance R
3
less than 0.01 &OHgr;·cm because of the limitation of the amount solution of Sb which can be in the solution.
Moreover, since it is impossible to make the impurity concentration in the substrate high because of the limitation of solution, it is difficult to get a good ohmic contact between an N-type substrate and an electrode.
On the other hand, in the method which utilizes gold as an electrode material, the barrier height of the gold for an P-type silicon substrate is 0.2 eV, and therefore so a good ohmic contact between those can be obtained. However, since the barrier height of the gold for an N-type silicon substrate is relatively high, 0.8 eV, the contact between those becomes a schottky contact and may have undesirable diode character.
Moreover, when an overall thickness is thick, stress from a package and a step between a lead frame and the source electrode
62
becomes higher. Therefore, the wire bonding work becomes very difficult. Also, the cost of gold is very high.
Techniques other than the aforementioned techniques have also been known. The technique which is disclosed in Japanese Unexamined Patent Publication 57-15420 suggests that a back surface of a silicon substrate is ground to improve adherence between the back surface and a collector electrode formed on the back surface. The technique which is disclosed in “IEEE ELECTRON DEVICE LETTERS, VOL. 10, NO. Mar. 3 1989, P101-103” suggests that a 0.004 &OHgr;·cm arsenic-doped silicon substrate is used.
SUMMARY OF THE INVENTION
An object of this invention is to reduce the ON-resistance of a semiconductor device.
Another object of this invention is to get a good ohmic contact.
A still further object of this invention is to provide a thin semiconductor device having the advantage of small stress from a package and easy wire bonding.
To accomplish the above objects, a semiconductor device according to this invention includes an N-type semiconductor substrate including arsenic as an impurity and having a ground surface formed on one surface thereof, said ground surface having concavo-convex irregularities, a first electrode formed on another surface other than said one surface of said N-type semiconductor substrate, a second electrode formed on said ground surface and ohmically contacted with said N-type semiconductor substrate through said ground surface, and a semiconductor element formed in said N-type semiconductor substrate and in which an electric current flows between said first electrode and said second electrode during an ON-state thereof.
REFERENCES:
patent: 4852345 (1989-08-01), Himelick
patent: 4859629 (1989-08-01), Reardon et al.
patent: 4879250 (1989-11-01), Chan
patent: 4927784 (1990-05-01), Kazior et al.
patent: 4931412 (1990-06-01), Fischer et al.
patent: 4985740 (1991-01-01), Shenai et al.
patent: 5241862 (1993-09-01), Okabe et al.
patent: 5338961 (1994-08-01), Lidow et al.
patent: 5689130 (1997-11-01), Okabe et al.
patent: 57-15420 (1982-01-01), None
patent: 57-097630 (1982-06-01), None
patent: 59/189625 (1984-10-01), None
patent: 59-213140 (1984-12-01), None
patent: 59-220937 (1984-12-01), None
patent: 59-113629 (1985-06-01), None
patent: 61-234041 (1986-10-01), None
patent: 61-296769 (1986-12-01), None
patent: 62/23170 (1987-01-01), None
patent: 62-43123 (1987-10-01), None
patent: 62-243332 (1987-10-01), None
patent: 62-293678 (1987-12-01), None
patent: 1-169970 (1989-07-01), None
patent: 58-45814 (1993-10-01), None
patent: 63-253633 (1998-10-01), None
Webster's II New Riverside University Dictionary, 1984, P,549.*
Semiconductor devices, physics and technology, by S. M. Sze, P, 38, 1985.*
Wolf et al., “Silicon Processing for the VLSI Era, vol. 1: Process Technology”, Lattice Press, 1986, pp. 14-15.*
Krishna Shenai, “
Kuroyanagi Akira
Okabe Yoshifumi
Yamaoka Masami
Denso Corporation
Harness Dickey & Pierce PLC
Loke Steven
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