Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-05
2002-10-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06463568
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the design of integrated circuits. More particularly, this invention describes a technique for generating compact data structures in integrated circuits.
BACKGROUND OF THE INVENTION
Conventional mapping, placing, and routing tools treat the entirety of a netlist as a homogeneous unit. The disadvantage of this approach is that the whole netlist is treated as having homogeneous characteristics—an assumption that is most often false. For example, a typical netlist comprises about 75% datapath, or “structured,” functions and about 25% random, or “unstructured,” functions. Most advanced methodologies are concerned with sophisticated ways to map, place, and route the unstructured functions, which represent the smaller proportion of the netlist. That is, the majority of a netlist is typically subjected to map, place, and route algorithms that have been optimized for the unstructured functions. This results in map, place, and route inefficiencies for the majority, structured portion of a netlist. This utilization inefficiency typically results in performance degradation.
Algorithms that do treat the structured portion of a netlist with any difference from the unstructured portion of a netlist are typically limited to arranging the structured portions according to simple, bit-sequential rules. For example, an object “A” may be arranged in a column such that its least and most significant elements are at opposite ends of the column. Typically, this arrangement is made without any regard for other structured objects. Specifically, another object “B” may be similarly arranged, but object “B” is not arranged by taking into account the structure of object “A”, and conversely, object “A” is not arranged by taking into account the structure of object “B.” Overall, this individual treatment of structured objects results in less than optimal map, place, and route results for the netlist as a whole.
In view of the foregoing, it would be highly desirable to use an algorithm that would recognize the structured portion of a netlist and apply to the whole structure an optimal map, place, and route results for the netlist as a whole.
SUMMARY OF THE INVENTION
A method of designing a circuit includes the step of establishing a matrix of circuit modules including sub-sets of circuit modules. A slice of circuit modules aligned along a first axis is selected from the matrix of circuit modules. The slice of circuit modules is replicated along a second axis to construct a logic structure with uniform height and width.
The invention provides a methodology for constructing a logic structure which will map, place, and route well. The technique of the invention takes advantage of the inherent regularity in a structured netlist to construct a logic structure optimal for mapping, placing, and routing. The invention generates a compact data structure, resulting in minimum resource consumption and maximum circuit performance. When applied to Field Programmable Logic Devices, the technique of the invention yields approximately 4:1 resource savings and a performance gain of approximately 10:1.
REFERENCES:
patent: 5543640 (1996-08-01), Sutherland et al.
patent: 5825662 (1998-10-01), Trimberger
patent: 5838954 (1998-11-01), Trimberger
patent: 5930499 (1999-07-01), Chen et al.
Morphics Technology Inc.
Siek Vuthe
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