Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-17
2002-12-31
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S758000
Reexamination Certificate
active
06501127
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a one-chip semiconductor device in which circuit elements of a peripheral circuit such as a logic circuit are integrated on one chip together with a nonvolatile memory-cell array, and also relates to a method of manufacturing the semiconductor device.
In most one-chip semiconductor devices having a nonvolatile memory-cell array, the similar wiring structure is used in the memory-cell array region and the other region for circuits other than the memory-cell array (hereinafter referred to as “peripheral circuits”) such as cell array driver circuits formed around the memory-cell array, logic circuits and SRAMs both formed around the cell-array driver circuits.
In the nonvolatile memories developed hitherto, one metal wiring layer or two metal wiring layers are provided in the memory-cell array region. The wires of the uppermost layer provided on the memory-cell array region have been finely patterned in accordance with design rules. These wires cause stepped portions of a passivation film formed on the wires. Thus, so called step coverage of the passivation film, i.e., protection film formed on the wires of the uppermost layer, is inevitably diminished.
FIG. 11
is a sectional view of a conventional nonvolatile memory device in which a two-layer wiring structure is used in both the memory-cell array region MR and the peripheral circuit region PR. A memory-cell array having nonvolatile memory cells MC is formed in the memory-cell array region MR of the silicon substrate
1
. Each of the memory cells MC has a floating gate FG and a control gate CG. Peripheral circuits are formed in the peripheral circuit region PR. Each peripheral circuit comprises MOS transistors Q of ordinary type, each having a source S, a drain D and a gate G.
As shown in
FIG. 11
, a first interlayer insulating film
2
is formed on the silicon substrate
1
and covers the memory cells MC and the MOS transistors Q. First-layer wires
3
are formed on the upper surface of the first interlayer insulating film
2
. A second interlayer insulating film
4
is provided on the first interlayer insulating film
2
and covers the first-layer wires
3
. Second-layer wires
5
are formed on the second interlayer insulating film
4
. A passivation film
6
acting as a protection film is formed on the second interlayer insulating film
4
and covers the second-layer wires
5
.
Contact metal such as tungsten are filled in via holes formed in the first interlayer insulating film
2
so that n
+
regions formed in the surface of the silicon substrate
1
and the first-layer wires
3
are connected with each other by contacts
17
. Further, via holes are formed to provide contacts
17
between the first-layer wires
3
and the second-layer wires
5
as shown in FIG.
11
.
As in most nonvolatile memories, the passivation film
6
is a silicon nitride film (hereinafter referred to as “plasma nitride film”) formed by means of plasma CVD method. The plasma nitride film
6
hardly allows passage of moisture, hydrogen or impurities such as positive mobile ions. However, this nitride film
6
is inferior to TEOS (Tetraethyloxysilane) film and SOG (Spin-On-Glass) film in terms of the step coverage. If the second-layer wires
5
are arranged at a short pitch of, for example, 0.4 micron line and space, the passivation film
6
will have thin portions
7
and voids
8
at the step portions between second-layer wires
5
as is illustrated in FIG.
11
. Each thin portion
7
formed at a step defined by a side of a wire
5
and the upper surface of the second interlayer insulating film
4
will fail to function as a passivation film perfectly. Mobile impurity ions such as sodium and humidity may pass through the thin portions
7
and first and second interlayer insulating films
2
and
4
from outside into the memory-cell array. This would lower the reliability of the memory-cell array, for example, endurance characteristics and data retention characteristics. The voids
8
are likely to hold contaminant including humidity and impurities during the manufacture of the nonvolatile memory device. If held in the voids
8
, the impurities and humidity included in the contaminant will adversely influence the memory-cell array.
Mobile impurity ions, hydrogen and humidity may enter the memory-cell array, in such a small amount that they would make no problems in ordinary MOS transistor circuits. Even if they exist in so small an amount, they will likely destroy data in the memory-cell array after the nonvolatile memory device has delivered to the user.
The memory device shown in
FIG. 11
may be a NOR-type flash memory device. If so, the first-layer wires
3
are used as bit lines in the memory-cell array region MR, while the second-layer wires
5
are used as wires backing word lines or bit lines or used as subsidiary wires for split signal lines of a word-line decoder or for the split bit lines.
If the second-layer wire
5
is used as word-line backing wire, each wire
5
may be used for one word line or a plurality of word lines. In the case where each wire
5
backs one word line, the wires
5
must be arranged at a short pitch. If so, the passivation film
6
will have many defects due to the degraded step coverage. Even if the pitch is relatively long, the step coverage of the passivation film
6
is insufficient at either side (i.e., step portion) of each wire
5
. Consequently, mobile impurity ions and humidity will pass through the defects formed in the passivation film
6
, eventually entering the memory-cell array.
As mentioned above, the similar wiring structure is used in the uppermost metal wiring layer of memory-cell array region MR and peripheral circuit region PR of the conventional nonvolatile memory device shown in FIG.
11
. Therefore, the passivation film
6
, i.e., the uppermost layer of the memory device, has defects, inevitably lowering the reliability of the memory-cell array. A decrease in the reliability of the cell array must be prevented. To this end, an insulating film may be formed on the second interlayer insulating film
4
, covering the second-layer wires
5
and having a flat upper surface, and the passivation film
6
may be formed on the upper surface of the insulating film. This results, however, in an increase in the number of manufacturing steps and, hence, an increase in cost.
In the conventional nonvolatile memory device, metal wires are provided above the memory-cell array. The metal wires block the ultraviolet rays applied to neutralize the memory cells. The greater the number of layers of wires provided, and the shorter the pitch at which the wires of each layer are arranged, the longer the time required to neutralize the memory-cell array.
Further, the greater the number of wires provided above the memory-cell array, the greater the charging damage affected to the nonvolatile memory cells in the process of manufacturing the nonvolatile memory device. The charging damage results from discharge of high-voltage static electricity that is generated during the wire forming process. Hence, the greater the number of layers of wires provided above the memory-cell array, the larger the charging damage.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of the above and has its object to provide a semiconductor device capable of being made at minimum cost and in which the wiring structure is improved to enhance the reliability of the memory-cell array. Another object of the invention is to provide a method of manufacturing the semiconductor memory device.
According to the first aspect of the present invention, there is provided a semiconductor memory device which comprises:
a semiconductor substrate having a first region and a second region located adjacent to the first region;
a memory-cell array including a plurality of nonvolatile memory cells provided in the first region of the semiconductor substrate;
a peripheral circuit formed of circuit elements other than the nonvolatile memory cells and provided in the second reg
Banner & Witcoff , Ltd.
Chaudhuri Olik
Doan Theresa T.
LandOfFree
Semiconductor device including a nonvolatile memory-cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including a nonvolatile memory-cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including a nonvolatile memory-cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2997136