Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-17
2002-10-01
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S307000
Reexamination Certificate
active
06459113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a system LSI incorporating DRAMs, a method of manufacturing the same, and a cell size calculation method for DRAM memory cells.
2. Description of the Prior Art
In recent years, a DRAM mixing or hybrid system LSI which integrates a logic such as processor, ASIC, or the like, and a large-scale DRAM on a common semiconductor substrate has been applied for many purposes. In such a system LSI, an internal data bus of multiple bits, e.g. 128-512 bits, makes an interconnection between the logic and the DRAM, thus achieving a data transmission speed which is higher by one to two orders, as compared to a case that a commercially available DRAM and a logic each having a small number of terminals are connected with each other on a common printed circuit board.
In addition, with respect to the logic, the number of external input pins may be reduced as compared to a system configuration which mounts externally the commercially available DRAMs. Further, a DRAM block is connected to a logic via an internal wiring inside the system LSI. Since the length of the internal wiring is sufficiently shorter than that of wirings on the printed circuit board, and also has a small parasitic impedance, charging and discharging currents can be drastically reduced, and signal transmissions can be carried out at high speed.
From these reasons, the DRAM hybrid system LSI has contributed greatly to the high performance of intelligence apparatuses that deal with a large amount of data of 3-D graphic processing, image and voice processing, and the like.
FIG. 17
is a schematic block diagram illustrating a configuration example of a conventional semiconductor integrated circuit device, which designates a DRAM mixing or hybrid system LSI. In
FIG. 17
, reference numeral
100
designates a power supply pin terminal for feeding power supply potential exVdd;
101
designates a large scale logic (LG);
102
designates an analog core (ACR);
103
designates a DRAM core (MCR);
104
designates a test interface circuit (TIC);
105
designates a first external pin terminal group (LPGA);
106
designates a second external pin terminal group (APG); and
107
designates a test pin terminal group (TPG).
The aforementioned system LSI includes: the large scale logic
101
, connected to the first external pin terminal group, for executing a commanded processing; the analog core
102
, connected between the large scale logic
101
and the second external pin terminal group
106
, for executing a processing of analog signals; the DRAM core
103
, connected to the large scale logic
101
via internal wirings, for storing data required by the large scale logic
101
; and a test interface circuit
104
for executing a test operation for the DRAM core
103
through the test pin terminal group
107
while separating the large scale logic
101
and the DRAM upon a test mode. The DRAM core
103
receives a power supply voltage exVDD via the power supply pin terminal
100
.
The analog core
102
includes a Phase-Locked Loop (PLL) for generating an internal clock signal; an analog/digital (A/D) converter for converting an externally inputted analog signal to a digital signal; and a digital/analog (D/A) converter for converting a digital signal supplied from the large scale logic
101
to an analog signal to be outputted.
FIG. 18
is a sectional schematic illustration taken along an arbitrary line in a large scale logic unit during a conventional DRAM-logic mixing process. In
FIG. 18
, reference numeral
201
designates a semiconductor substrate;
202
designates a first interlayer dielectric;
203
a
and
203
b
each designate a second interlayer dielectric;
204
designates a third interlayer dielectric;
205
designates a fourth interlayer dielectric;
206
designates a cover film;
211
designates a word line;
221
designates a bit line;
222
designates a first metal wiring;
223
designates a second metal wiring;
224
designates a third metal wiring;
231
designates a via plug such as tungsten W;
241
designates a contact hole;
242
designates a first through hole for connecting the first metal wiring
222
with the second metal wiring
223
; and
243
designates a second through hole for connecting the second metal wiring
223
with the third metal wiring
224
.
In
FIG. 18
, an n-channel or p-channel MOS transistor is first formed on the semiconductor substrate electrically separated by trench isolation. The gate electrode is formed by a wiring layer made of a silicon containing material, for example, polysilicon doped with an impurity or doped polysilicon, polycide such as tungsten silicide (WSix), and the like, and serves as the word line
211
through a microfabrication.
Metal wiring layers for multilevel metallization are formed by a metal such as aluminum Al or an alloy containing copper Cu therein on the upper layer of the MOS transistor with interposing the first to fourth interlayer dielectrics
202
-
205
. These wiring layers are micro-fabricated independently to form the first metal wiring
222
, second metal wiring
223
, and third metal wiring
224
.
These metal wirings
222
-
224
are electrically connected to the wiring layer of the bit line
221
formed by a material such as tungsten via the via plug
231
in which tungsten W or the like is buried in the contact hole
241
and through holes
242
and
243
.
Note that the above-described bit line
221
is not required in a perfect CMOS logic process which mixes no DRAMs.
FIG. 19
is a schematic diagram of a memory cell array section of a DRAM core in a conventional semiconductor integrated circuit device, and
FIG. 20
is a sectional schematic illustration taken along an arbitrary line in the longitudinal direction of the memory cell array of FIG.
19
. In
FIG. 19
, reference numeral
301
designates a cell plate electrode CP;
302
designates a storage node contact;
303
designates a bit line contact;
305
designates a sense amplifier S/A;
310
designates a sub-word driver range (odd);
311
designates a sub-word driver range (even);
315
and
316
designate main word lines MWL<i> and MWL<i+1> (i=natural number), respectively; BL and ZBL designate a non-inversion bit line and an inversion bit line, respectively; and WL designates a word line, which connects with the main word line MWL via the logic gate.
The memory cell is typically composed of a capacitor for storing an electric charge and a field effect transistor (FET) or MOS transistor operating as a cell selection switch, and is called one transistor type. The gate electrode of this transistor is connected to the word line WL which feeds a selection signal of the memory cell, and controls the opening and closing of the memory cell. On the other hand, the drain of the transistor is connected to the bit lines BL and ZBL for cell information intake which are wired perpendicularly to the word line WL, and exchanges of data between memory cell and read or write circuit will be carried out through the drain.
In
FIG. 20
, the reference numeral
401
designates a semiconductor substrate
401
;
402
designates a trench isolation region;
403
designates a word line;
403
a
designates a transistor gate wiring;
405
designates a configuration dummy bit line;
406
designates a bit line;
407
designates a storage node;
408
designates a cell plate electrode CP;
409
a
,
409
b
, and
411
each designate a contact buried by a via plug made of tungsten W;
410
designates a first metal wiring serving as a main word line;
412
designates a second metal wiring serving as a VCP power supply line;
421
designates a first interlayer dielectric;
422
a
and
422
b
each designate a second interlayer dielectric; and
423
designates a third interlayer dielectric.
Incidentally, a capacitor dielectric is formed between the storage node
407
and the cell plate CP
408
, and these components construct a stacked capacitor to store a signal electric charge.
Th
Arimoto Kazutami
Morihara Toshinori
Shimano Hiroki
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Wilson Allan R.
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