Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2000-08-04

2002-12-10

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S408000, C257S409000

Reexamination Certificate

active

06492680

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. Besides, the present invention relates to a field effect semiconductor integrated circuit and particularly to a semiconductor integrated circuit device for outputting a high accuracy current, used for EL element driving, LED driving, or the like.
2. Description of the Related Art
FIG. 2
shows an example of a schematic circuit diagram of a MOS transistor constituting an output circuit of a conventional semiconductor integrated circuit device.
In the semiconductor integrated circuit device including a first transistor
10
for switching an output current and a second transistor
20
for varying an output current value, which are electrically connected in series between an external output terminal
40
of the output circuit shown in
FIG. 2 and a
power source voltage terminal
1
, a potential converted to a desired voltage by two dividing resistors
70
a
provided in series between the power source voltage terminal
1
and a GND terminal
50
is supplied as a gate potential of the second transistor
20
.
It is conventionally well known that in this output circuit, the output current value fluctuates due to manufacture fluctuation in the threshold voltage of the second transistor
20
, manufacture fluctuation in the resistance value of the dividing resistor
70
a,
and the like.
Thus, there has been used a method in which the dividing resistor
70
a
is made a variable resistor and is adjusted later, or a voltage directly controlled from an external connection terminal is applied as the gate potential of the second transistor
20
.
Besides, the second transistor
20
has been no function for relieving manufacture fluctuation in the current value.
FIG. 10
shows an example of a conventional MOS semiconductor device. For making the drawing easily viewable, a passivation film and the like are omitted.
In
FIG. 10
, a gate electrode
209
is formed on an N-type semiconductor substrate
201
through a gate insulating film
206
, and a MOS semiconductor element is constituted by P
+
source/drain regions
202
and
203
, P
−
source/drain regions
204
and
205
having an impurity concentration lower than the P
+
source/drain regions
202
and
203
, and first insulating films
207
and
208
having a thickness larger than the gate insulating film. The P
+
source/drain regions
202
and
203
are connected to first metal wirings
213
and
214
through contact holes
211
and
212
and through an interlayer insulating film
210
. The P
−
source/drain regions
204
and
205
are made short within the range where photolithography technique, high withstand voltage characteristic, or the like permits, so that an increase in an area of the MOS semiconductor element is prevented.
However, in the conventional semiconductor integrated circuit device, there have been problems as follows:
In the case of the insulated gate field effect semiconductor integrated circuit device shown in
FIG. 2
, since the output current value fluctuates due to the manufacture fluctuation in the threshold voltage of the second transistor
20
, the manufacture fluctuation in the resistance value of the dividing resistor
70
a,
and the like, there has been adopted such a method that the dividing resistor
70
a
is made the variable resistor, or the gate potential of the second transistor
20
is directly controlled from the external connection terminal, as described above. However, the method includes many factors to increase the cost, such as trouble of varying the resistor, or trouble of inputting a potential with high accuracy from the outside for every IC chip including the circuit shown in FIG.
2
.
Moreover, since the second transistor
20
has a large current driving capacity, there has been a defect that when the threshold voltage or the like fluctuates, the output current is also greatly changed.
Besides, in the prior art shown in
FIG. 10
, variation in drain current is large due to fluctuation in bias applied to the gate electrode, which is not preferable.
SUMMARY OF THE INVENTION
Then, the present invention uses the following means to solve the foregoing problems.
A semiconductor integrated circuit device includes a first MOS transistor for switching an output current and a second MOS transistor for varying an output current value, which are electrically connected in series between an output terminal of an output circuit and a power source voltage terminal, wherein a fuse trimming circuit is provided to a gate electrode of the second MOS transistor.
Besides, the one fuse trimming circuit is provided for every eight circuits each being the output circuit.
Besides, the one fuse trimming circuit is provided for every circuits integer times as many as eight circuits each being the output circuit.
Further, in the second MOS transistor, a gate electrode is provided through a gate oxide film in the vicinity of the surface of a semiconductor substrate, a source side low concentration impurity region and a drain side low concentration impurity region are provided through a thick oxide film at lower sides of both end portions of the gate electrode in a channel direction, the source side low concentration impurity region is provided from the lower side of the gate electrode toward the outside to have a length nearly equal to a channel length, a source region is provided to be connected with an end portion of the source side low concentration impurity region, the drain side low concentration impurity region is provided further toward the outside from the lower side of the gate electrode, and a drain region is provided to be connected with an end portion of the drain side low concentration impurity region.
Besides, the source side low concentration impurity region is provided to have a length of 3 &mgr;m to 50 &mgr;m.
Besides, the drain side low concentration impurity region is provided to have a length of approximately {fraction (1/10)} to ⅕ of the length of the source side low concentration impurity region.
In order to solve the foregoing problems, the P
−
source region of the MOS semiconductor element is lengthened, so that variation in drain current due to fluctuation in gate bias is made small.
By the foregoing structure, the variation in the drain current to the gate bias becomes small, and constant current output characteristics of the MOS semiconductor element can be stabilized.


REFERENCES:
patent: 5181090 (1993-01-01), Maruo
patent: 5436482 (1995-07-01), Ogoh
patent: 5656518 (1997-08-01), Gardner et al.
patent: 5965921 (1999-10-01), Kojima
patent: 6054743 (2000-04-01), Maekawa
patent: 6146952 (2000-11-01), Nariman et al.

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