Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-11-01
2002-12-03
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000
Reexamination Certificate
active
06489652
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a trench DMOS (double-diffused metal oxide semiconductor) device.
DESCRIPTION OF PRIOR ART
Conventionally, a trench DMOS transistor comprises, as shown in
FIG. 1
, a trench passing through a body layer
11
formed over an n-type semiconductor substrate
10
, said body layer
11
being formed of a p-type diffused region and a more heavily doped p
+
region, a gate oxide layer
24
formed on the sidewalls and bottom of the trench, a gate polysilicon layer
26
formed over said gate oxide layer
24
in the trench, and an n
+
-type source impurity layer
28
formed on both side surfaces of the gate polysilicon layer
26
and partially at the top surface of the body layer
11
.
In such trench DMOS transistors, the drain terminal is connected to the semiconductor substrate
10
, the source terminal is connected to the source impurity layers
28
and the body layer
11
, and the gate terminal is connected to the polysilicon layer
26
in the trench. The semiconductor substrate
10
comprises a heavily doped n
+
-type silicon substrate
10
a
covered with a low doped n-type covering layer
10
b.
During operation of the device, two channels are formed along the interface surfaces between the gate oxide layer
24
and the body layer
11
.
Such conventional DMOS transistors may suffer a breakdown phenomenon which occurs in the junction between the heavily doped region of the body layer
11
and the low doped covering layer
10
b,
or between the gate oxide layer
24
and the low doped covering layer
10
b
when the transistor is reverse-biased. The latter case may be recoverable, but the former case is not, so there is a problem with the reliability of a device fabricated in this manner. In order to resolve this problem, U.S. Pat. No. 5,298,442, incorporated by reference herein, proposes that the junction between the heavily doped region of the diffused layer (i.e. the body layer)
11
and the low doped covering layer
10
b
be formed below the trench so that the breakdown may occur through the gate oxide layer
24
to the heavily doped region
11
.
U.S. Pat. No. 4,992,390, incorporated by reference herein, proposes that the bottom of the gate oxide layer
24
be formed more thickly in order to prevent a breakdown in the gate oxide layer
24
. This process and structure are described below with reference to
FIGS. 2A
to
2
D.
Referring to
FIG. 2A
, a first oxide layer
12
, a nitride layer
14
, and a second oxide layer
16
are sequentially formed on a semiconductor substrate
10
. A patterned photoresist
18
is formed on the second oxide layer
16
to define a trench forming region. As shown in
FIG. 2B
, an etching process is performed using the patterned photoresist
18
as a trench forming mask. Thus, the laminated layers on the substrate
10
are sequentially removed by the etching process, and a portion of the substrate
10
is selectively removed to form the trench
19
. Oxygen ion implantation is performed to implant oxygen ions in the bottom of the trench
19
.
Thereafter, an oxidation process is carried out to form the gate oxide layer
24
on the sidewalls and bottom of the trench, as shown in FIG.
2
C. In this case, the gate oxide layer
24
is formed more thickly on the bottom of the trench than on the sidewalls because of the previous oxygen ion implantation. Removal of the nitride layer
14
and the second oxide layer
16
results in the structure shown in FIG.
2
D. Hence, the above described breakdown is prevented from occurring in the region between the gate oxide layer
24
and the semiconductor substrate
10
.
Another conventional means for preventing breakdown is described in U.S. Pat. No. 5,298,442, incorporated by reference herein, and is described below with reference to
FIGS. 3A
to
3
F. In
FIG. 3A
, a first oxide layer
12
, a nitride layer
14
and second oxide layer
16
are sequentially formed on a semiconductor substrate
10
. A patterned photoresist
18
is formed on the second oxide layer
16
by means of a well-known photo process to define the trench forming region. An etching process is carried out by using the patterned photoresist
18
as a trench forming mask to remove the layers to form the trench
19
, as shown in FIG.
3
B. After removal of the patterned photoresist
18
, a nitride layer
20
is deposited on the sidewalls and bottom of the trench
19
and on the second oxide layer
16
, as shown in
FIG. 3C. A
third oxide layer
22
is formed over the nitride layer
20
by means of thermal oxidation.
As shown in
FIG. 3D
, a reactive ion etching process is performed on the oxide layer
22
to form spacers
22
a
on the sidewalls of the trench
19
. The spacers
22
a
are used as a mask for removing the exposed nitride layer
20
on the second oxide layer
16
and exposed at the bottom of the trench
19
. This is followed by an oxidation process to produce a thick oxide layer
24
in the region defined by the spacers
22
a,
as shown in FIG.
3
E. Finally, the spacers
22
a
and the nitride layers
14
and
20
are all removed. This is followed by an oxidation process to produce the gate oxide layer
24
a
with the bottom region being thicker than the sidewalls, as shown in FIG.
3
F. Hence, breakdown is prevented from occurring in the thick bottom region
24
a
shown in FIG.
3
F.
The prior art described above suffers from several drawbacks. In
FIG. 2D
, the gate oxide layer
28
with a consistent thickness through the bottom region may not prevent the breakdown which frequently occurs in the central portion of the bottom region. In
FIG. 3F
, the gate oxide layer
24
a
with the bottom region gradually sloped from the central portion to the boundary portions may degrade the silicon interface characteristics because it is formed by using a dry etching process to produce the oxide spacers
22
a
on the sidewalls of the trench, as shown in FIG.
3
E. In addition, the whole process is complicated due to the additional processing steps of forming and removing the oxide spacers
22
a.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a trench DMOS device which prevents the breakdown from occurring in the central portion of the bottom of the gate oxide layer, and to simplify the fabrication process for producing such a device.
It is another object of the present invention to provide a trench DMOS device or a trench semiconductor device with a gate oxide layer having an improved structure.
According to an embodiment of the present invention, a trench DMOS device comprises a trench formed in a semiconductor substrate, a gate polysilicon layer formed in said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than the sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than the boundary regions thereof.
According to another embodiment of the present invention, there is provided a method of fabricating a trench DMOS device, which comprises the steps of forming a trench by selectively etching a semiconductor substrate, said trench having sidewalls and bottom; forming a thermal oxide layer on the sidewalls and bottom; filling a polysilicon layer into said trench; wet-etching said thermal oxide layer between said polysilicon layer and said sidewalls from the top of said trench to a point surpassing the bottom of said polysilicon layer, said thermal oxide layer comprising a bottom part of having a thickness greater than each of sidewall parts, and said bottom part comprising a central region having a thickness greater than each of boundary regions thereof; and performing, after removal of said polysilicon layer, a thermal oxidation to form a relatively thin oxide layer on said thermal oxide layer on said sidewalls of said trench and on a top surface of said semiconductor substrate, said thermal oxide layer and said relatively th
Jang Young-Soo
Jeon Chang-Ki
Fairchild Semiconductor Corporation
Nadav Ori
Thomas Tom
Townsend and Townsend / and Crew LLP
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