Method of forming contact plug of semiconductor device

Details Method of forming contact plug of semiconductor device Method of forming contact plug of semiconductor device

2002-02-22

2002-10-01

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S672000, C438S745000

Reexamination Certificate

active

06458692

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming contact plugs of a semiconductor device.
2. Description of the Related Art
As techniques for manufacturing semiconductor devices develop and the applications for memory devices expand, memory devices having large capacity have been developed. In particular, a memory cell is typically composed of one capacitor and one transistor, and thus dynamic random access memories (DRAMs) are advantageous in that their integration density has been remarkably improved.
As the integration density of semiconductor devices increases, the size of contact holes decreases, but the thickness of interlayer dielectric layers increases. Thus, the aspect ratio of the contact holes, i.e., the ratio of a hole's length to its diameter, increases and an arrangement margin of the contact holes decreases in a photolithography process. Thus, it is difficult to manufacture semiconductor devices. As a result, a technique for forming contact pads is widely used. Moreover, a technique for forming self-aligned contact pads has been proposed as a technique for forming contact pads appropriate for realizing grand-scale integrated semiconductor devices.
An increase in the capacitance of capacitors used in semiconductor devices is also required, and thus, a structure in which capacitors are formed over bit lines, i.e., a capacitor-over bit line (COB) structure, has been adopted. However, as the integration density of semiconductor devices increases, when forming a buried contact, such as a contact formed underneath a storage electrode of the capacitor and connected to the storage electrode and a source of a transistor, the buried contact may be electrically short-circuited with a bit line formed underneath the capacitor. In order to prevent such a short-circuit, a dielectric margin of an interlayer dielectric layer insulating the bit line must be ensured. That is, the size of the contact must decrease. However, the amount of reduction in the size of the contact is restricted due to the limitations of the photolithography process used in creating the device.
FIGS. 1 through 5
are cross-sectional views showing steps of forming contact plugs of a semiconductor device according to the prior art. Referring to
FIG. 1
, a cell area A and a core area B are defined in a semiconductor substrate
100
. Field oxide layers (not shown), which electrically isolate active regions from each of the cell area A and the core area B, are formed. The field oxide layers may be formed by a common local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) process.
Transistors having source regions (not shown), drain regions (not shown), and gate electrodes (not shown) are formed in the cell area A and the core area B. The gate electrodes include gate oxide layers, gate conductive layers, and capping dielectric layers, and spacers are formed on the sidewalls of the gate electrodes. The source and drain regions have a lightly doped drain (LDD) structure.
A first interlayer dielectric layer
102
is deposited over the resultant structure and is then planarized by chemical mechanical polishing (CMP) or etch back. The first interlayer dielectric layer
102
is patterned to form contact pads
104
which are electrically connected to the source/drain regions. A conductive layer is deposited to fully fill the first interlayer dielectric layer
102
and is then planarized by CMP. Node-separation is made by the planarization process, and thus, the contact plugs
104
are formed over the source/drain regions.
A second interlayer dielectric layer
106
is formed over the resultant structure and is then planarized by CMP or etch back. Contact holes penetrating the second interlayer dielectric layer
106
are formed using a common photolithography process or an etching process and are then filled with a conductive material, thereby forming contact plugs (not shown) for connecting bit lines and the drain regions. The contact plugs are connected to the contact pads
104
over the drain regions.
Bit lines
112
are formed on the second interlayer dielectric layer
106
. The bit lines
112
are connected to the contact plugs. The bit lines
112
have a structure in which conductive layers
108
and capping dielectric layers
110
are sequentially stacked. The capping dielectric layers
110
are formed of silicon nitride.
A silicon nitride layer is deposited over the resultant structure and is then etched by an anisotropic method, thereby forming spacers
114
on the sidewalls of the bit lines
112
.
Referring to
FIG. 2
, a third interlayer dielectric layer
116
is deposited over the resultant structure. As the integration density of semiconductor devices increases, the width between the bit lines
112
is reduced and the aspect ratio of the bit lines
112
is increased. In the case of increasing the aspect ratio, voids occur at the entrance of a gap between the bit lines
112
. Then, adjacent conductive layers are short-circuited, and thus, the semiconductor device does not operate normally. In order to solve this problem, the entrance of the gap is widened by a wet etching and then a fourth interlayer dielectric layer
118
is deposited as shown in FIG.
3
. The deposited interlayer dielectric layer
118
is planarized by CMP or etch back.
Referring to
FIG. 4
, a photoresist pattern
120
is formed using a photolithography process to form contact holes for electrically connecting a storage electrode (not shown) and source regions. The fourth interlayer dielectric layer
118
, a third interlayer dielectric layer
116
a,
and the second interlayer dielectric layer
106
are sequentially dry-etched using the photoresist pattern
120
as a mask, thereby forming contact holes
112
. However, the capping dielectric layers
110
and the spacers
114
are also removed during the dry etching. As a result, the conductive layers
108
of the bit lines
112
are exposed. Then, the conductive layers
108
are electrically short-circuited with contact plugs (
124
of FIG.
5
), and thus, the semiconductor device does not operate normally. Only the fourth, third, and second interlayer dielectric layers
118
,
116
a,
and
106
are selectively etched using an etching gas having an excellent etch selectivity to a silicon nitride layer, but the silicon nitride layer is also etched at a predetermined ratio during the etching process. Thus, upper portions of the capping dielectric layers
110
and the spacers
114
are etched. As a result, the conductive layers
108
are exposed. This phenomenon becomes more serious as the contact holes
122
become deeper. In
FIG. 4
, dotted lines denote portions where the capping dielectric layers
110
and the spacers
114
are removed during the etching process for forming the contact holes
122
.
Referring to
FIG. 5
, the photoresist pattern
120
is removed. A polysilicon layer, which is doped with ions, is deposited over the resultant structure to fully fill the contact holes
122
and is then planarized by CMP or etch back. Contact plugs
124
, which are node-separated, are formed due to the planarization process. However, as described previously, conductive layers
108
a
and contact plugs
124
are contacted, and thus, may be electrically short-circuited if the conductive layers
108
a
are exposed. Also, a capping dielectric layer
110
a
in the core area B is entirely consumed due to dishing during the planarization process for node-separating and thus, the conductive layer
108
a
may be exposed. In
FIG. 5
, dotted lines denote portions where the capping dielectric layer
110
a
and spacers
114
a
in the core area B are removed.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is an object of the present invention to provide a method of forming contact plugs of a semiconductor device which can effectively remove voids due to the deposition of interlayer dielectric layers, reduce parasitic capacitance,

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