Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-09-13
2002-12-10
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S686000, C257S669000, C257S783000, C257S700000
Reexamination Certificate
active
06492715
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to integrated semiconductor packages comprising a chip, interposer, and substrate, and more particularly to improvements to the structural and environmental integrity thereof.
2. Description of Prior Art
Semiconductor devices and other electronic components, such as chip carriers, have been mounted to circuitized substrates, such as printed circuit boards, using a variety of methods, including conductive pins, solder balls (commonly referred to as bumps), wirebonds, and the like. In certain applications, an IC chip is mounted directly to the substrate through the aforementioned mounting methods. However, in applications requiring high wiring density it is common to employ an interconnect member between the IC chip and the substrate in order to cost effectively increase the number of I/Os the device is capable of handling. These interconnect members are commonly referred to as interposers.
Chip packages used in high density applications are well known. A common example of such a package is what is referred to in the art as “ball grid array” packages (“BGAs”). These types of packages include an IC chip having a lower surface on which is mounted an array of electrical contacts, commonly in the form of solder bumps, which serve as the I/O leads. These solder bumps must be electrically connected to pads positioned on the upper surface of the substrate, but due to the small spaces between contacts, wiring the substrate to accommodate all the solder bumps is cost prohibitive. Moreover, such connections are not structurally sound due to the thermal expansion characteristics of the substrate and chip structures which cause deflections in the members and consequently, breaks in the electrical connections.
To remedy the drawbacks of directly connecting the IC chip to the substrate, an interposer having a hierarchy of wiring densities is commonly employed. The interposer is commonly composed of a thin film, such as polyimide. Single and multiple layer thin film interposers are well known in the art. One known method for manufacturing multiple layer thin film interposers is by dispersing a first layer of polyimide on a carrier plate, typically composed of glass, forming vias, or micro-holes through this polyamide dielectric layer in a predetermined patterns, and then depositing copper or other conductive wire leads thereon by sputtering, plating, or other known methods. A second layer (and subsequent layers) of polyimide is then built upon the preceding dielectric layer. Vias are then formed through the dielectric layer, and conductive wires are formed thereon. The manufacturing of these types of thin film interposers is well known in the art. The interposer is then positioned on the substrate with the conductive pads on the interposer being in electrical communication with corresponding ones of the pads formed on the substrate. A process, such as reflow soldering, or the like, may then be employed to melt the solder and form an electrical bond at the conductive pads between the interposer and substrate. The glass carrier plate is then removed from the top surface of the interposer through a known process, such as a laser ablation process as described in the present assignee's prior U.S. Pat. No. 5,258,236. The IC chip (which may be in the form of a BGA) is then positioned on the upper surface of the interposer with its I/O contacts in electrical communication with the conductive pads formed on the upper surface of the interposer. A heating process is then employed to melt the solder and form a bond between the electrical contacts on the chip and interposer.
Manufacturing a module comprising a single chip, interposer and substrate can be readily modified to include mounting multiple chips on a single interposer, or multiple interposers on a single substrate.
3. Objects and Advantages
It is a principal object and advantage of the present invention to provide an electronic package or module comprising a chip, interposer, and substrate that is structurally and environmentally sound.
It is an additional object and advantage of the present invention to provide an electronic package or module that is cost effectively manufactured.
It is a further object and advantage of the present invention to provide an electronic package or module that can effectively handle an increased number of I/Os per unit area.
Other objects and advantages of the present invention will in part be obvious, and in part appear hereinafter.
SUMMARY OF THE INVENTION
In accordance with the foregoing objects and advantages, the present invention provides an integrated semiconductor module comprising a chip, interposer, and substrate. The module is adapted to be mounted on a traditional circuit card carrying multiple other components.
The chip of the present invention can be a conventional IC chip or chip package, including ball grid array packages, and will simply be referred to hereinafter as a “chip.” The interposer of the present invention is a conventional thin film interposer, such as those composed of a polyimide material and fabricated on a glass carrier plate. The substrate of the present invention is a conventional circuitized substrate, such as a BGA or laminate substrate, that is commonly employed in carrying a chip on a circuit card.
In its assembled state, the present invention comprises an interposer mounted on top of a substrate with the electrical contacts formed on the lower surface of the interposer positioned in electrical communication with respective ones of electrical contacts formed on the upper surface of the substrate. A non-conductive material, such as an epoxy resin, fills the voids between the interposer and substrate created by the electrical connections. The epoxy resin forms a mechanical bond between the interposer and substrate, thereby enhancing the structural integrity of the unit. Moreover, by filling the voids between the electrical connections, essentially no foreign particles can become entrapped therein and cause electrical malfunctions. Accordingly, the environmental and operational integrity of the unit is also enhanced.
A chip is mounted to the upper surface of the interposer with its I/O connectors (in the form of solder balls, wire leads, etc . . . ) positioned in electrical communication with the electrical contacts formed on the upper surface of the interposer. A non-conductive material, such as an epoxy resin, fills the voids created between the interposer and chip by the electrical contacts, thereby enhancing the structural and environmental integrity of the unit.
REFERENCES:
patent: 4752027 (1988-06-01), Gschwend
patent: 4925723 (1990-05-01), Bujatti et al.
patent: 5067007 (1991-11-01), Kanji et al.
patent: 5211805 (1993-05-01), Srinivasan
patent: 5468681 (1995-11-01), Pasch
patent: 5525204 (1996-06-01), Shurboff et al.
patent: 5534466 (1996-07-01), Perfecto et al.
patent: 5576519 (1996-11-01), Swamy
patent: 5598036 (1997-01-01), Ho
patent: 5759047 (1998-06-01), Brodsky et al.
patent: 5843811 (1998-12-01), Singh et al.
patent: 5863815 (1999-01-01), Egawa
patent: 5912507 (1999-06-01), Dunn et al.
patent: 5918113 (1999-06-01), Higashi et al.
patent: 5962925 (1999-10-01), Eifuku et al.
patent: 6002168 (1999-12-01), Bellaar et al.
patent: 6075710 (2000-06-01), Lau
patent: 6137164 (2000-10-01), Yew et al.
patent: 05029390 (1993-02-01), None
patent: 06291165 (1994-10-01), None
patent: 07249732 (1994-10-01), None
patent: 09064236 (1997-07-01), None
patent: 11008334 (1999-01-01), None
patent: 11049595 (1999-02-01), None
patent: 11265967 (1999-09-01), None
S.W. Anderson, F.E. Andros, A.C. Bhatt, P.A.Chalco, S.K. Kang and C.J. Sambucetti,IBM Technical Disclosure Bulletin, vol. 40, No. 2, Feb. 1997.
G.A. Huston, P.D. Isaacs, G.A. Knotts and M. Swain,IBM Technical Disclosure Bulletin, vol. 37 No. 11, Nov. 1994.
Markovich Voya R.
Powell Douglas O.
Sarkhel Amit K.
Hancock & Estabrook, LLP
Huynh Andy
International Business Machines - Corporation
McGuire George R.
Nelms David
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