Data output circuit for semiconductor device with level...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S333000, C326S063000, C326S083000

Reexamination Certificate

active

06501306

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to data input/output circuits, and more particularly to a data output circuit for a semiconductor device.
2. Description of the Prior Art
Recently, a larger number of CMOS transistors have been integrated on a silicon chip in proportion to a higher complexity of a semiconductor integrated circuit. In order to reduce power consumption and increase operating speed, an internal supply voltage of the chip is on a decreasing trend, for example, from 5V to 3.3V, 2.5V or less. In this regard, an internal supply voltage generation circuit has been provided in a typical integrated circuit chip such as a semiconductor memory chip for dropping an external supply voltage to generate a voltage necessary to internal circuits of the chip. To the contrary, a relatively high voltage has been required in increasing the capability of interfacing with external devices of the chip and the capability of driving specific internal transistors of the chip. To this end, a boosting circuit has often been employed in the integrated circuit chip for boosting the external supply voltage to provide the boosted voltage to desired circuits such as a word line.
A semiconductor device with the above internal supply voltage generation circuit has needed a data output circuit operable according to various external supply voltage levels to provide a suitable fit between internal signal interface levels and those of external devices. The data output circuit of the semiconductor device typically comprises an output buffer, high-impedance control circuit and output driver. The data output circuit further comprises a level shifter for voltage level conversion in addition to the above components. The level shifter is typically adapted to convert the level of output data with an internal supply voltage level into an external supply voltage level and transfer the resultant output data to an output terminal.
In the above output data circuit for the semiconductor device, the output buffer provides a primary output data signal pair, which is applied to the high-impedance control circuit for the generation of a secondary output data signal pair. Subsequently, the generated secondary output data signal pair is converted in voltage level by the level shifter and then transferred as the final output data externally through the output driver. However, the above-mentioned output data circuit has encountered various problems in output operation such as, for example, a low data output speed, a low high-impedance transition speed and an output signal skew occurring in pull-up and pull-down operations, which will be more clearly recognized from the following detailed description taken in conjunction with the preferred embodiments of the present invention.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a data output circuit for a semiconductor device which is capable of solving the above problems.
It is another object of the present invention to provide a data output circuit which is capable of increasing or maximizing a data output speed and a high-impedance transition speed.
It is a further object of the present invention to provide a data output circuit which is capable of minimizing a skew between output signals in pull-up and pull-down operations.
It is yet another object of the present invention to provide a level shifting circuit which is capable of increasing or maximizing a data output speed and a high-impedance transition speed while maintaining an excellent driving capability and a low leakage current characteristic.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by a provision of a data output circuit for a semiconductor device, the data output circuit comprising an output buffer for receiving and latching an input data signal with a first voltage range in response to a clock control signal to provide a pair of output data signals; high-impedance controller/level shifter means for outputting high-impedance drive data for the control of a high impedance state through a pair of output lines according to a first logic state of a high-impedance control signal and for receiving the output data signal pair from the output buffer according to a second logic state of the high-impedance control signal and transferring a pull-up output data signal and a pull-down output data signal through the output lines, with each of the pull-up and pull-down output data signals having a second voltage range broader than the first voltage range; and an output driver for maintaining a data output terminal at a high impedance state in response to the high-impedance drive data from the high-impedance controller/level shifter means and for performing an output driving operation in response to the pull-up and pull-down output data signals from the high-impedance controller/level shifter means to output final data externally through the data output terminal.
In accordance with another aspect of the present invention, there is provided a method for outputting data in a semiconductor device, comprising the steps of receiving and latching an internal input data signal with a first voltage range in response to a clock control signal to provide a pair of output data signals; level-shifting the output data signals using a level shifter while a high-impedance control signal maintains a first logic state, transferring the level-shifted signals respectively as pull-up and pull-down output data signals with a second voltage range broader than the first voltage range and applying the output data signals directly to the level shifter to generate high-impedance drive data for the control of a high impedance state, when the high-impedance control signal becomes a second logic state; and maintaining a data output terminal at a high impedance state in response to the high-impedance drive data and performing an output driving operation in response to the pull-up and pull-down output data signals to output final data externally through the data output terminal.


REFERENCES:
patent: 5414379 (1995-05-01), Kwon
patent: 5627487 (1997-05-01), Keeth
patent: 5723986 (1998-03-01), Nakashiro et al.
patent: 6107830 (2000-08-01), Okumura
patent: 6292025 (2001-09-01), Okumura

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