Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-04
2002-12-31
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S353000, C257S354000
Reexamination Certificate
active
06501133
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-367945, filed Nov. 30, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to, for example, a SOI (Silicon on Insulator) semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Recently it is demanded that semiconductor integrated circuits should operate at lower power consumption and at higher speed. It is therefore desirable to lower the power-supply voltage and make the elements smaller in each semiconductor integrated circuit. At present, SOI-type elements attract much attention, because they are superior to the bulk-type elements hitherto used, in terms of low parasitic capacitance and low sub-threshold coefficient.
If a MISFET (Metal Insulator Semiconductor FET) is made smaller, the width of its gate sidewall will decrease, regardless of the structure of the substrate. Consequently, the characteristic of the MISFET is noticeably deteriorated due to the short-channel effect. The short-channel effect can be readily controlled if the MISFET has a shallow source/drain region.
To decrease the junction capacitance and junction leakage current, it is desirable to form the MISFET in a SOI substrate and set the bottom of the source/drain region in contact with a buried insulating film. If the source/drain region is s hallow, however, the layer in which the channel region is provided is proportionally thin. The MISFET inevitably becomes a fully depleted element. In any fully depleted element it is difficult to control the threshold voltage, as will be explained below in detail.
FIGS. 19 and 20
show two general semiconductor devices, each formed in a SOI substrate. In
FIGS. 19 and 20
, the identical components are designated at the same reference numerals.
As shown in
FIGS. 19 and 20
, the SOI substrate comprises a silicon substrate
1
, a buried insulating film (BOX: Buried Oxide)
2
, and a single-crystal silicon active layer
3
. The buried insulating film
2
is a silicon oxide film that is provided on the silicon substrate
1
. The single-crystal silicon active layer
3
is provided on the buried insulating film
2
.
As
FIG. 19
shows, a gate insulating film
5
is provided on the silicon active layer
3
of the substrate
1
. A gate electrode
6
is formed on the gate insulating film
5
. A sidewall insulating film
8
is mounted on the sides of the gate electrode
6
. A source/drain extension region
7
and a source/drain region
9
are provided in the silicon active layer
3
. The regions
7
and
9
have the conductivity type opposite to that of the silicon active layer
3
. Both regions
7
and
9
have been formed by implanting, for example, impurity ions into the silicon active layer
3
.
The device shown in
FIG. 19
is a MISFET. The MISFET is a partially depleted SOI element. In this SOI element, the silicon active layer
3
is comparatively thick. The junction between the source/drain region
9
and the silicon active layer
3
lies at a level higher than the bottom of the silicon active layer
3
. Hence, a depletion layer is formed in the bottom part of the source/drain region
9
, as indicated by a broken line in FIG.
19
. This increases the junction capacitance. Moreover, carriers move through the trap in the depletion layer, possibly generating a leakage current.
The device shown in
FIG. 20
is a fully depleted SOI element. As
FIG. 20
shows, the silicon active layer
3
is so thin that the source/drain region
9
contacts the buried insulating film
2
. A depletion layer is formed in that part of the silicon active layer
3
that lies below the gate electrode
6
. The device is therefore a fully depleted SOI element. The threshold voltage of the fully depleted SOI element varies with the thickness of the silicon active layer
3
. In view of this, it is difficult to control the threshold voltage.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor device which comprises: an element-forming layer formed on a buried insulating film of a semiconductor substrate; a gate insulating film formed on the element-forming layer; a gate electrode formed on the gate insulating film; and a source region and a drain region formed in the element-forming layer and located on two sides of the gate electrode, respectively. The buried insulating film has a first part and a second part. The first part of the buried insulating film is located below the source and drain regions. The second part of the buried insulating film is located below the gate electrode thinner than the first part. The source and drain regions have bottoms which contact the first part of the buried insulating film.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an element isolation region in an element-forming layer which is insulated from a semiconductor substrate by a buried insulating film; forming a masking material on a channel-forming part of the element-forming layer; implanting oxygen ions into the element-forming layer, by using the masking material; performing a heat treatment, thereby making a first part of the buried insulating film thicker, into which the oxygen ions have been implanted and which lies on the sides of the channel-forming part; removing the masking material and forming a gate insulating film on the element-forming layer; forming a gate electrode on the gate insulating film; and forming a source region and a drain region in two parts of the element-forming layer which lie on the sides of the gate electrode, respectively, the source and drain regions having bottoms which contact the first part of the buried insulating film.
REFERENCES:
patent: 5614729 (1997-03-01), Ukai et al.
patent: 5920097 (1999-07-01), Horne
patent: 5955767 (1999-09-01), Liu et al.
patent: 6100159 (2000-08-01), Krivokapic
patent: 6130457 (2000-10-01), Yu et al.
patent: 6174754 (2001-01-01), Lee et al.
patent: 6287901 (2001-09-01), Christensen et al.
patent: 6303412 (2001-10-01), Park
Kabushiki Kaisha Toshiba
Ngo Ngan V.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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