Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-17
2002-11-26
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S014000, C438S015000, C438S017000, C438S018000, C438S106000, C438S118000
Reexamination Certificate
active
06486051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more specifically, to placement of active circuitry underneath bonding pads.
2. Background Information
Integrated circuit chips (dice) are manufactured by fabricating a plurality of identical circuits on a semiconductor wafer, scribing the wafer between the circuits, and subsequently breaking apart the wafer into individual chips. The chips are then mounted on lead frames or substrates for packaging and wire bonded for chip external connections. The bonding wire connects the bonding pads on the chip with the lead frame. IC chips can be bonded using thermocompression or ultrasonic techniques. In thermocompression bonding, heat and pressure are applied to the pad and to the underlying substrate in order to achieve the bond. In ultrasonic bonding, sufficient energy is supplied by ultrasonic vibration in order to achieve the bond.
Active circuit elements, including transistors, resistors, capacitors, inductors, and the like, are generally located in the central portion of the semiconductor device, while bonding pads have been located around the periphery of the active region on the chip. Bonding pads are generally not located above the active circuits in order to protect the active circuit elements during bonding processes.
In many instances, it may be desirable to place resistive circuits beneath the bonding pads. For example, it may advantageous to place resistive circuits under bonding pads in order to decrease die area and to reduce parasitic resistance due to long interconnection wires between bonding pads and active regions. However, due to thermal and mechanical stresses occurring during the bonding process, the underlying resistive circuits may become damaged. For example, as the wire and the die are heated during the process of connecting the wire to the bonding pad, the bonding wire is pressed onto the bonding pad. Additional energy may be supplied by ultrasonic vibration in order to form the bond. Pressure and vibration exerted upon the bonding pad may cause microfractures and/or subtle dislocations of the under-bonding-pad resistive structure which may impact the electrical performance of the resistor or may impact its long-term reliability.
Therefore, what is needed is a method for placing a wire resistor beneath an active bonding pad in an integrated circuit device, without damaging or otherwise affecting the performance of the resistive circuit.
SUMMARY OF THE INVENTION
A method for relieving bonding stress in an integrated circuit device having an active circuit placed under a bonding pad is disclosed. The active circuit is formed above a silicon substrate, the active circuit comprising a wire pattern. A dielectric layer is deposited over the wire pattern. A bonding pad is formed over the dielectric layer.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.
REFERENCES:
patent: 4636832 (1987-01-01), Abe et al.
patent: 4984061 (1991-01-01), Matsumoto
patent: 5502337 (1996-03-01), Nozaki
patent: 5689428 (1997-11-01), Sauerbrey et al.
patent: 5751065 (1998-05-01), Chittipeddi et al.
Chang Jung-Yueh
Gross William J.
Sabin Gregory D.
Anya Igwe U.
Blakely , Sokoloff, Taylor & Zafman LLP
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