Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-08-06
2002-12-10
Ho, Hoai (Department: 2815)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S203000, C365S230060
Reexamination Certificate
active
06493275
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor integrated circuit device incorporating a MIS (Metal Insulator Semiconductor) transistor. More particularly, the present invention relates to a measure to reduce electromagnetic radiation intensity.
Conventionally, it is known that electronic equipments generate unwanted electromagnetic radiation called EMI (Electromagnetic Interference) radiation. It is desired that this EMI radiation be as small as possible due to its possible interference with operation of another electronic equipment. Therefore, the EMI radiation intensity is subjected even to the legal controls. The EMI radiation is generated due to various causes, but operating characteristics of a huge number of transistors included in LSI (Large Scale Integration) of the electronic equipment, particularly MOS (Metal Oxide Semiconductor) transistors in a CMOS (Complementary Metal-Oxide Semiconductor) integrated circuit, are an important cause. A switching waveform of the MOS transistor includes high-frequency components due to an abrupt change in voltage and current. Accordingly, a portion serving an antenna within the electronic equipment generates unwanted electromagnetic radiation according to such an abrupt change.
In the frequency range up to several tens of gigahertz (GHz), a semiconductor integrated circuit device itself has low EMI radiation intensity because it has few portions serving as an antenna. However, when a semiconductor chip, i.e., a semiconductor integrated circuit device, is mounted on a printed circuit board or a package, power supply lines and signal lines having several to several tens of centimeters are extended therein. Thus, these power supply lines and signal lines serve as an antenna, increasing the EMI radiation intensity. Moreover, the EMI radiation intensity largely depends on a mounting form. It is preferable to avoid a mounting form that has a large number of portions serving an antenna as much as possible. In general, in order to reduce the EMI radiation intensity, a pattern shape of the power supply and signal lines on the printed circuit board is changed, or a part having a function to suppress a high-frequency current such as ferrite beads is incorporated. However, these methods are often based on the empirical rule. Therefore, prediction of the effect is difficult, and the costs are also increased. Accordingly, it is preferable to reduce the EMI radiation at the MOS transistor level in the semiconductor integrated circuit device, thereby ensuring the flexibility of mounting forms without considering the EMI radiation.
In particular, the MOS transistors in the recent CMOS semiconductor integrated circuit devices have an increased operation speed as a result of the progress in miniaturization technology. This causes ever-increasing EMI radiation intensity due to an increased switching operation speed, i.e., rise and fall time, of the MOS transistors. In this respect as well, means for effectively reducing the EMI radiation in connection with the operating characteristics of the MOS transistors has been greatly demanded.
The following methods have been proposed for reducing the EMI radiation in connection with the operation characteristics of the MOS transistors in the semiconductor integrated circuit device:
(1) Optimize the transistor size. More specifically, the rising/falling rate of a voltage waveform (which is referred to as “slew rate”) is reduced as much as possible in order to reduce harmonic components of the frequency included in a voltage amplitude. Alternatively, the slew rate and maximum amplitude of a current waveform in the switching operation of the transistors are reduced in order to suppress the intensity of electromagnetic waves generated from a power supply line and the like;
(2) Avoid simultaneous switching of the transistors. More specifically, the delay time is adjusted so as to disperse the switching time of the transistors, thereby reducing concentrated generation of electromagnetic waves (EMI radiation) from a power supply line due to simultaneous switching. Thus, the EMI radiation intensity from the power supply line and the like is reduced; and
(3) Using a spread spectrum clock system, i.e., technology of reducing the EMI radiation by frequency modulation of a clock signal, to suppress the intensity of electromagnetic waves generated from the clock system.
The spread spectrum clock system is the technology of varying a clock frequency (fc) by a small amount (&dgr;) in a period of a modulation frequency (fm), and thus diffusing the energy distribution of harmonic EMI radiation of the clock in a high-frequency region, thereby reducing the peak value of the EMI radiation. This technology is widely used in the recent CMOS semiconductor integrated circuit devices, and is described in, e.g., U.S. Pat. No. 5,488,627 titled “Spread Spectrum Clock Generator and Associated Method”. For example, the use of the spread spectrum clock system enables reduction in electric field intensity of the EMI radiation by about 10 dB by, e.g., setting the modulation frequency (fm) to 50 KHz, i.e., about 0.5% of the clock frequency (fc) of the frequency shift (&dgr;). It is known that the harmonic intensity distribution of the clock in the high-frequency region has a width of about &dgr;, and the profile thereof is determined by time variation of &dgr; in a period of 1/fm (which is referred to as modulation profile). In general, clock-related circuitry includes a clock generation circuit for generating a clock signal, and a clock buffer for distributing the generated clock to each circuit within the integrated circuit. In the spread spectrum clock system, a frequency-modulated clock is generated by the clock generation circuit, and then supplied from the clock buffer to each circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to implement a semiconductor integrated circuit device generating reduced EMI radiation while operating at a high speed, by finely dispersing the rise and fall of each MOS transistor by using relatively simple design and structure in view of operating characteristics of the MOS transistors in the semiconductor integrated circuit device.
According to the present invention, a semiconductor integrated circuit device integrating a plurality of MIS (Metal Insulator Semiconductor) transistors each having its source and drain provided in a respective region of a semiconductor substrate that is surrounded by a substrate region, and its gate provided on a region of the semiconductor substrate that is located between the source and drain, wherein the plurality of MIS transistors include at least one of a P-channel modulation MIS transistor and an N-channel modulation MIS transistor, a modulation substrate bias Vb varying with a prescribed amplitude within such a range that causes no latch-up is applied to the P-channel modulation MIS transistor, and a modulation substrate bias Vb′ varying with a prescribed amplitude within such a range that causes no latch-up is applied to the N-channel modulation MIS transistor.
Thus, in response to application of the modulation substrate bias to the substrate region of the modulation MIS transistor, a threshold voltage and current driving capability of the modulation MIS transistor vary with time within the range that causes no latch-up. Accordingly, a logic threshold voltage, delay time, and rise and fall time of an output waveform of, e.g., a complementary logic gate including the modulation MOS transistor are modulated, whereby energy spectrum of electromagnetic waves radiated during signal transition has a larger peak width than that in the case where there is no modulation. Accordingly, the peak value and thus the EMI radiation intensity are reduced while maintaining a proper operation of the semiconductor integrated circuit device.
Preferably, in the aforementioned semiconductor integrated circuit device, the modulation substrate bias Vb varying with the prescribed amplitude within a range of Vb≧Vdd−Vf is
Ho Hoai
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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