Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-18
2002-12-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06496968
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a wiring method for an implementation design of a semiconductor integrated circuit (IC), and in particular, to a hierarchical wiring method suitable for a hierarchical implementation design in which lower and upper hierarchical layers are employed to hierarchically design a configuration of the semiconductor integrated circuit.
In the hierarchical implementation design of a semiconductor integrated circuit, when a block is implemented in a lower hierarchical layer (inter-block wiring), wirings between terminals, i.e., block edge terminals of a net to be connected to external terminals external to the blocks, and the external terminals, that is, external wirings including inter-block wirings are not ordinarily established since terminal positions as the connecting destinations outside the block are not determined in this stage. The net indicates in this specification wirings connecting equipotential terminals to each other.
Assume in the operation that a wiring pattern in the inter-block net is generated, for example, to enclose a block edge terminal and blocks are thereafter arranged in an upper layer of a chip or the like. In this situation, there arises a problem when a block in the upper layer is to be connected to the block in the lower layer. Namely, it is impossible to draw or to elongate a wiring pattern from the block edge to a position outside the block.
To solve this problem, JP-A-8-129574 describes a technology broadly known as an example of the conventional technology concerning the hierarchical implementation method for a semiconductor integrated circuit.
In the technology of JP-A-8-129574, the wiring is conducted in a chip layer as an upper layer prior to the intra-block wiring. Wiring pattern data used in this operation is supplied to the block implementation, namely, the wiring pattern is not used in the intra-block wiring to thereby guarantee that a wiring pattern is drawn from a block edge in a chip implementation.
SUMMARY OF THE INVENTION
The prior art requires the determination of block positions in the chip before the block implementation. Consequently, each time the block layout is altered in the chip, the intra-block wiring is required to be changed and hence the implementation design time is elongated.
It is therefore an object of the present invention to provide a wiring method which solves the conventional problem above and in which when achieving the intra-chip wiring in a hierarchical implementation design for a semiconductor integrated circuit (chip) including high-density wiring layers, wiring pattern spaces to block edge terminals are guaranteed while preventing increase in delay and deterioration in a wiring ratio due to a wiring detour between an inter-block net as well as elongation of the implementation design time. The wiring ratio indicates a ratio of actual wirings to the number of nets to be wired.
To achieve the object above, a hierarchical wiring method is provided in accordance with an aspect of the present invention. The method comprises, when achieving a hierarchical wiring of a semiconductor circuit in a hierarchical implementation design of the semiconductor integrated circuit, a step of extracting, when wiring an intra-block net to establish connections in a block in a lower layer, block edge terminals for terminals of a net to be connected to a position external to the block, a step of defining a rectangle circumscribing the block and determining the rectangle as a boundary of the block, a step of disposing, on four edges of the block, virtual terminals connected to block edge terminals, a step of automatically conducting wirings, prior to another net, between the block edge terminals to the associated virtual terminals thus disposed, automatically wiring thereafter all remaining intra-block nets, and a step of deleting, after the intra-block wirings are completely finished, all wiring patterns of nets connected to the virtual terminals disposed.
In accordance with another aspect of the present invention, there is provided a hierarchical wiring method for a semiconductor integrated circuit in a hierarchical implementation design of the semiconductor integrated circuit. The method includes, to wire an intra-block net to establish connections in a block in a lower layer when a plurality of wiring layers are provided, a step of extracting block edge terminals as terminals of a net to be connected to a position external to the block in the lower layer, a step of generating at least one virtual terminal of the block edge terminals in an upper layer in the proximity of the block edge, a step of automatically establishing wirings between the block edge terminals to the associated virtual terminals prior to another intra-block net, a step of automatically wiring thereafter all remaining intra-block nets by use of only wiring layers lower than the upper layer in which the virtual terminal is generated, and a step of deleting, after the intra-block wirings are completely finished, all wiring patterns of nets connected to the virtual terminals.
REFERENCES:
patent: 4688070 (1987-08-01), Shiotari et al.
patent: 4964057 (1990-10-01), Yabe
patent: 4974049 (1990-11-01), Sueda et al.
patent: 5231589 (1993-07-01), Itoh et al.
patent: 406045443 (1994-02-01), None
Hongyo Katsuaki
Mogaki Masato
Yamada Hiromitsu
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lin Sun James
Siek Vuthe
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