Semiconductor device and method for manufacturing the same

Details Semiconductor device and method for manufacturing the same Semiconductor device and method for manufacturing the same

2001-08-07

2002-11-12

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S294000, C438S454000

Reexamination Certificate

active

06479330

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with field-shield isolation structure and a method for manufacturing the same.
2. Description of the Background Art
FIG. 44
is a plan view of a background-art semiconductor device with field-shield isolation structure. In this figure, defining an active region AR of a MOS transistor, a field-shield (FS) gate electrode
1
is formed like a rectangular ring to make a field-shield isolation structure and a gate electrode
2
of the MOS transistor is formed above the FS gate electrode
1
so as to halve the FS gate electrode
1
.
The active regions AR externally located on both sides of the gate electrode
2
are regions to serve as source/drain (S/D) regions
3
and above the S/D regions
3
, S/D electrodes
4
mainly made of aluminum are formed. A plurality of contact holes
5
are formed between the S/D regions
3
and the S/D electrodes
4
.
Further, insulating layers are provided between the FS gate electrode
1
and the gate electrode
2
and between the S/D region
3
and the S/D electrode
4
, but not shown in this figure, for convenience of illustration, to allow main elements to be clearly seen.
FIG. 45
is a cross section taken along the lines A—A of
FIG. 44
, showing a construction of the MOS transistor and the FS gate electrode formed on a bulk silicon substrate.
In this figure, the gate electrode
2
is formed on a surface of a silicon substrate SB. The gate electrode
2
has a gate oxide film
21
formed on the surface of the silicon substrate SB, a polysilicon layer
22
formed on the gate oxide film
21
and a salicide layer
23
formed on the polysilicon layer
22
, and side wall oxide films
24
are formed on the side surfaces of these film and layers. In the surface of the silicon substrate SB outside each side of the gate electrode
2
, an S/D layer
31
and a lightly doped drain (LDD) layer
32
which constitute the S/D region
3
are provided. A salicide layer
33
covers the surface of the S/D layer
31
.
On the surface of the silicon substrate SB outside the S/D region
3
, the FS gate electrode
1
is formed. The FS gate electrode
1
has an FS gate oxide film
11
formed on the surface of the silicon substrate SB, a polysilicon layer
12
formed on the FS gate oxide film
11
and an FS upper oxide film
13
formed on the polysilicon layer
12
, and side wall oxide films
14
are formed on the side surfaces of these films and layer. Furthermore, in some cases, the construction of the FS gate electrode
1
is referred to as a field-shield isolation structure and the polysilicon layer
12
is referred to as an FS gate electrode.
An interlayer insulating film
9
is formed so as to cover the FS gate electrode
1
, the gate electrode
2
and the S/D region
3
. A contact hole
5
is formed, penetrating the interlayer insulating film
9
between the S/D region
3
and the S/D electrode
4
and filled with conductor, to thereby electrically connect the S/D region
3
and the S/D electrode
4
to each other.
Next, with reference to
FIGS. 46
to
51
, a manufacturing process will be discussed. First, the FS gate oxide film
11
, the polysilicon layer
12
and the FS upper oxide film
13
are layered on the silicon substrate SB (implanted with channel) in this order. With a resist mask R
1
, a patterning is performed on the multiple layers as shown in
FIG. 46
, to form the FS gate electrode
1
. The FS gate oxide film
11
is formed by CVD (=Chemical Vapor Deposition) at the temperature of 700° C. to have a thickness of 100 to 1000 Å. The polysilicon layer
12
is formed by CVD at the temperature of 600 to 800° C. to have a thickness of 100 to 1000 Å. The polysilicon layer
12
is implanted with phosphorus (P) of about 1×10
20
/cm
3
as impurity. The FS upper oxide film
13
is formed by CVD, for example, at the temperature of 700° C. to have a thickness of 500 to 2000 Å.
In the step of
FIG. 47
, after removing the resist mask R
1
, the side wall oxide film
14
is formed. The process for forming the side wall oxide film
14
is as follows: an oxide film is formed so as to cover the FS gate electrode
1
and then the oxide film is selectively removed by anisotropic etching (dry etching), to form the side wall oxide film
14
being self-aligned. In this case, however there is a problem of damage due to the anisotropic etching left at a region X on the surface of the silicon substrate SB in FIG.
47
. This problem will be discussed later in detail with reference to
FIGS. 56 and 57
.
Subsequently, the gate oxide film
21
is formed on the surface of the silicon substrate SB and the polysilicon layer
22
is formed so as to cover the gate oxide film
21
and the FS gate electrode
1
. Then, as shown in
FIG. 48
, a resist mask R
2
is formed at a predetermined position on the polysilicon layer
22
and a patterning is performed on the polysilicon layer
22
through the resist mask R
2
.
In the step of
FIG. 49
, with the polysilicon layer
22
used as a mask, the LDD layer
32
is formed, being self-aligned, by ion implantation. In this ion implantation, arsenic (As) or phosphorus (P) is injected at an energy of 30 to 70 KeV at a dose of 1×10
13
to 4×10
14
/cm
2
. The ion injection should be continuously performed at an injection angle of 45° to 60°, with the silicon substrate rotated.
Subsequently, as shown in
FIG. 50
, the side wall oxide film
24
is formed on the side wall of the gate electrode
2
. The process for forming the side wall oxide film
24
is as follows: an oxide film having a thickness of 500 to 800 Å is formed so as to cover the gate electrode
2
and then the oxide film is selectively removed by anisotropic etching (dry etching), to form the side wall oxide film
24
being self-aligned.
After that, with the FS gate electrode
1
and the gate electrode
2
used as a mask, the S/D layer
31
is formed by ion implantation. In this ion implantation, arsenic (As) or phosphorus (P) is injected at an energy of 30 to 70 KeV at a dose of 4×10
14
to 7×10
15
/cm
2
.
Subsequently, as shown in
FIG. 51
, the salicide films
23
and
33
are formed, being self-aligned, only on the upper surface of the gate electrode
2
and the surface of the S/D region
3
. These salicide films
23
and
33
may be any of cobalt silicide, titanium silicide, tungsten silicide or the like.
After that, the interlayer insulating film
9
is formed so as to cover the FS gate electrode
1
, the gate electrode
2
and S/D region
3
, the contact hole
5
is formed so as to penetrate the interlayer insulating film
9
on the S/D region
3
and filled with the conductor, and the S/D electrode
4
mainly made of aluminum is formed thereon, to obtain the background art semiconductor device with field-shield isolation structure as shown in
FIGS. 44 and 45
.
Next, a cross section taken along the lines B—B of
FIG. 44
is shown in FIG.
52
. In this figure, the gate oxide film
21
is formed on the surface of the silicon substrate SB between two FS gate electrodes
1
, and the polysilicon layer
22
is formed so as to cover the gate oxide film
21
and the FS gate electrodes
1
. Further, the salicide film
23
is formed on the polysilicon layer
22
. Furthermore, in the silicon substrate SB beneath the gate oxide film
21
, a channel region is created when the device operates.
The interlayer insulating film
9
is formed so as to cover the FS gate electrode
1
, the gate electrode
2
and the S/D region
3
, and the contact hole
5
is formed so as to penetrate the interlayer insulating film
9
located on the end portion of the gate electrode
2
and filled with the conductor, to connect the gate electrode
2
and a gate interconnection layer
6
.
A manufacturing process will be discussed below with reference to
FIGS. 53
to
55
. First, the FS gate oxide film (field-shield oxide film)
11
, the polysilicon layer
12
and

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