Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-03-07
2002-12-24
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S154000, C438S162000, C438S295000, C438S229000
Reexamination Certificate
active
06498057
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods and silicon-on-insulator (SOI) semiconductor structures for implementing transistor source connections using buried dual rail distribution.
DESCRIPTION OF THE RELATED ART
Fabricating smaller, more densely packed devices having greater computing capability is a continuing objective in building semiconductor devices. Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology are leading to the development of more complex and faster computer integrated circuits that operate with less power.
Silicon on insulator technology incorporates a buried insulator just below the transistors. Performance of silicon on insulator transistors is increased due to reduced diffusion capacitance and due to the floating body effect resulting in lower threshold voltages as compared to bulk silicon devices.
It is necessary to connect transistor source terminals to a power rail, ground GND or VDD in building semiconductor structure for silicon-on-insulator (SOI) transistor devices. Traditionally, in bulk silicon devices transistor source terminal connections are accomplished by using metal wires surrounded by oxide above the field effect transistors (FETs). These wires are then connected to the source terminals using vertical studs made of electrically conducting material. The power wires consume significant area on the semiconductor structure metal levels.
U.S. Pat. No. 5,889,306, issued Mar. 30, 1999 to Christensen et al., and assigned to the present assignee, discloses a semiconductor device including a conductive substrate, an insulator layer, a silicon layer doped with impurities and forming a first transistor and a second transistor, an isolation volume between the first transistor and the second transistor, and a conductive stud extending from the doped silicon layer to the substrate. One exemplary embodiment uses the bulk silicon substrate as a ground or power source for a semiconductor device such as a field effect transistor (FET). In a more preferred mode, a highly doped substrate is used, fabricated from a bulk silicon wafer of typical thickness. The substrate may function as either a ground plane or a power source, (such as a Vdd plane). In this manner, the substrate eliminates a very large percentage of the metal wiring used for power distribution. For example, the majority of ground wires are eliminated by connecting all electrically grounded transistor devices to the bulk silicon substrate. This connection may be made with a buried conductive stud. The conductive stud generally extends from the active silicon layer through the insulator layer to electrically contact the thick, low resistivity bulk silicon substrate below. With silicon on insulator (SOI) technology, traditional processing techniques may be used throughout fabrication of the device. The resulting device comprises electrical connections between the respective transistor regions and the highly conductive bulk silicon substrate. In turn, the substrate functions as a low resistance conductor between the devices. A single metal connection from an external ground or power source to the substrate may be used for multiple devices. The density of wiring across the surface of the device may also be reduced by a connection every several millimeters across the device surface which reduces the wires previously used for ground or power distribution.
U.S. Pat. No. 6,121,659, issued Sep. 19, 2000 to Christensen et al., and assigned to the present assignee, discloses a semiconductor-on-insulator integrated circuit with buried patterned layers as electrical conductors for discrete device functions, thermal conductors, and/or decoupling capacitors. A SOI semiconductor device has a conductive silicon substrate with a first volume doped with an n+ type dopant and a second volume doped with a p+ type dopant, an insulator layer of silicon dioxide, a silicon layer doped with impurities forming a first transistor and a second transistor having an isolation volume between the first transistor and the second transistor. A first conductive stud electrically connects the first transistor to the first volume. A second conductive stud electrically connects the second transistor to the second volume. Ground wires can be eliminated by connecting all electrically grounded transistor devices to the bulk silicon substrate using a buried conductive stud. The conductive stud generally extends from the active silicon layer through the insulator layer to electrically contact the thick, low resistivity bulk silicon substrate below. Thermal conductance is provided to reduce heating effects which reduce the switching speeds of active devices, such as transistors. Decoupling capacitance is provided between buried layers having different dopants and, hence, different voltage levels.
U.S. Pat. No. 6,287,901, issued Sep. 11, 2001 to Christensen et al., and assigned to the present assignee, discloses a method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.
A need exists for an effective mechanism in building SOI technology semiconductor structures for fabricating transistor source terminal connections to GND or VDD and that reduces the required area on the semiconductor structure metal levels.
SUMMARY OF THE INVENTION
Principal objects of the present invention are to provide an improved method and semiconductor structure for implementing transistor source connections for silicon-on-insulator (SOI) transistor devices. Other important objects of the present invention are to provide such method and semiconductor structure for implementing transistor connections substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined buried conduction layer to be connected to a SOI transistor source, and an intermediate conduction layer between the SOI transistor and the predefined buried conduction layer. A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silicide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An insulator is disposed between the second hole and the intermediate conduction layer. A conductor is deposited in the first and second holes to create a transistor source connection to the predefined buried conduction layer in the SOI semiconductor structure.
In one method of the invention, a thin layer of insulator is deposited over an interior of the etched holes. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from the bottom of the holes exposing the predefined buried conduction layer in the SOI semiconductor structure with the thin insulator layer covering sidewalls of the holes
Christensen Todd Alan
Sheets, II John Edward
Uhlmann Gregory John
Chaudhuri Olik
Huynh Yennhu B.
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