Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-29
2002-12-31
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S332000, C257S302000, C438S259000, C438S270000
Reexamination Certificate
active
06501129
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-093461, filed Mar. 30, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a semiconductor device having a high breakdown voltage and a method of manufacturing the particular semiconductor device.
FIG. 7
is a cross sectional view showing a conventional power (high breakdown voltage) vertical type MOSFET having a trench gate structure. A trench gate structure that permits improving the channel density is widely employed in a power vertical MOSFET in order to improve the on-voltage characteristics. As shown in
FIG. 7
, an N-type epitaxial semiconductor layer is formed on a first main surface (upper surface) of an N-type silicon semiconductor substrate
111
. Formed in the N-type epitaxial semiconductor layer are an N-type drain region (N
−
-type drain region)
106
, a P-type base region
105
, and an N-type source region (N
+
-type source region)
104
. The P-type base region
105
is formed in a surface region of the N-type drain region
106
. The N-type source region
104
is formed in a surface region of the P-type base region
105
. Each of the P-type base region
105
and the N-type source region
104
is formed by an impurity diffusion. A gate trench is formed in a manner to extend from the surface of the N-type source region
104
through the N-type source region
104
and the P-type base region
105
so as to reach the N-type drain region
106
. A gate insulating film
107
consisting of, for example, a silicon oxide film is formed on the side wall and the bottom of the gate trench. A gate electrode
108
made of, for example, a polycrystalline silicon (polysilicon) is buried in the gate trench. The gate insulating film
107
and the gate electrode
108
are covered with an interlayer insulating film
103
consisting of, for example, a silicon oxide film. A barrier metal layer
102
is formed on the entire substrate surface including the interlayer insulating film
103
. A source electrode
101
consisting of a metal electrode such as aluminum is formed on the source region
104
and the base region
105
with the barrier metal layer
102
interposed therebetween, and the source region
104
and the base region
105
are electrically connected to each other. A drain electrode
112
, which is a metal electrode, is formed on a second main surface (back surface) of the semiconductor substrate
111
.
FIG. 7
shows a unit cell portion of a semiconductor device, which corresponds to a unit cell portion of a semiconductor device in
FIG. 9
, as represented by region A in FIG.
9
. Incidentally, the semiconductor device shown in
FIG. 9
is for the exemplifying purpose. Therefore, the construction shown in
FIG. 7
is not necessarily equal to the construction of the unit cell portion of the semiconductor device shown in FIG.
9
. Similarly,
FIG. 8
shows a unit cell portion of another conventional semiconductor device.
In the conventional power vertical MOSFET having a trench gate structure as shown in
FIG. 7
, the impurity concentration is increased in the epitaxial silicon semiconductor layer
106
formed on the silicon semiconductor substrate
111
in order to lower the on-voltage. A depletion layer is generated if a reversed bias is applied between the source electrode and the drain electrode. If the impurity concentration in the epitaxial silicon semiconductor layer
106
is increased, a depletion layer
113
is generated as shown in the drawing. As denoted by arrows in the drawing, the electric field is concentrated in the corner portion of the trench because of the presence of the depletion layer. It should be noted that the Vdss breakdown voltage is deteriorated by the electric field concentration occurring in the corner portion of the trench.
FIG. 8
is a cross sectional view showing a conventional power MOSFET of a planar structure. As shown in the drawing, an N-type epitaxial semiconductor layer (N-type drain region)
106
is formed on a first main surface (upper surface) of an N-type silicon semiconductor substrate
111
. A P-type base layer
105
is formed in a surface region of the N-type drain region
106
. Also, an N-type source region
104
is formed in a surface region of the P-type base region
105
. A gate insulating film
107
such as a silicon oxide film is formed on the N-type source region
104
, the P-type base region
105
and the N-type drain region
106
except the region where a source electrode is to be formed. Also, a gate electrode
108
made of, for example, polysilicon is formed on the gate insulating film
107
. The gate insulating film
107
and the gate electrode
108
are covered with an interlayer insulating film
103
such as a silicon oxide film. A source electrode
101
, which is a metal electrode made of, for example, aluminum, is formed on the N-type source region
104
and the P-type base region
105
so as to electrically connect the N-type source region
104
to the P-type base region
105
. Further, a drain electrode
112
is formed on a second main surface (back surface) of the semiconductor substrate
111
.
In the conventional power MOSFET of the planar structure shown in
FIG. 8
, the impurity concentration is also increased in the epitaxial silicon semiconductor layer
106
formed on the silicon semiconductor substrate
111
in order to lower the on-voltage, as in the power vertical MOSFET of the trench gate structure shown in
FIG. 7. A
depletion layer is generated when a reverse bias is applied between the source electrode and the drain electrode. If the impurity concentration is increased in the epitaxial silicon semiconductor layer
106
, the electric field is concentrated in the extending portion of the P-type base region
105
. It should be noted that the Vdss breakdown voltage is deteriorated by the electric field concentration taking place in the extending portion of the P-type base region
105
.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention, which has been achieved in view of the situation described above, is to provide a semiconductor device in which the electric field concentration is relaxed in the corner portion of the trench gate or in the extending portion of the base region so as to improve the breakdown voltage and a method manufacturing the particular semiconductor device.
The present invention is featured in that formed in a part of the base region is an impurity diffusion region extending in a vertical direction of the semiconductor substrate and having an impurity concentration lower than that in the other portion of the base region. The impurity concentration of the impurity diffusion region is an average value of the concentration of the impurities diffused in the base region excluding the extending region. By forming the impurity diffusion region of a low impurity concentration, it is possible to extend the depletion layer toward the base region so as to improve the breakdown voltage. In the present invention, a trench is formed in a part of the base region, and an impurity of the conductivity type equal to that of the base region is introduced into the side wall and the bottom portion of the trench by ion implantation in a concentration lower than that in the base region, followed by diffusing the implanted impurity so as to form the impurity diffusion region of the low impurity concentration.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a semiconductor layer of a first conductivity type formed on one main surface region of the semiconductor substrate; a drain region of the first conductivity type formed in the semiconductor layer of the first conductivity type; a base region of a second conductivity type formed in a surface region of the drain region; a source re
Huynh Andy
Kabushiki Kaisha Toshiba
Oblon, Spivak, McClellland, Maier & Neustadt, P.C.
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