Method to reduce photoresist contamination from silicon...

Details Method to reduce photoresist contamination from silicon... Method to reduce photoresist contamination from silicon...

2001-08-21

2002-12-03

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S680000, C438S681000

Reexamination Certificate

active

06489238

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of semiconductor devices and fabrication and more specifically to a method for reducing photoresist contamination from silicon carbide films.
BACKGROUND OF THE INVENTION
To increase the operating speed, high performance integrated circuits use copper interconnect technology along with low dielectric constant dielectrics. Currently the damascene method is the most widely used method for forming copper interconnects. In the damascene method trenches are first formed in dielectric layers above the silicon wafer. The trenches are then filled with copper which form the electrical interconnects between the electronic devices which comprise the integrated circuit. In most instances it is beneficial to use a hardmask when etching the trenches required for the damascene method. This is illustrated in FIGS.
1
(
a
)-
1
(
b
).
Shown in FIG.
1
(
a
) is a dielectric layer
10
on which a hardmask layer
20
was formed. A photoresist layer
30
was formed and patterned on the hardmask layer
20
and used as a mask to etch an opening
35
in the hardmask layer
20
as shown in FIG.
1
(
a
). Following the removal of the photoresist layer
30
, the hardmask layer
20
is used as a mask to etch a trench in the dielectric layer
10
as shown in FIG.
1
(
b
). A major drawback to the use of hardmasks however is resist contamination or resist poisoning (hereafter referred to as resist poisoning). An example of resisting poisoning is shown in FIGS.
2
(
a
) and
2
(
b
).
As shown in FIG.
2
(
a
) a patterned photoresist layer
50
is formed over a hardmask layer
40
and a dielectric layer
10
. Due to resist poisoning, the width of the exposed pattern in the photoresist layer
52
is greater that the width of the pattern transferred to the hardmask
54
. This difference is due to the poisoning of the photoresist close to the hardmask layer. As a result of the resist poisoning effect, the width of the trench in the dielectric layer
54
will be less than the desired trench width
52
. This distortion of trench width can result in a degradation in the performance of the integrated circuit. There is therefore a need for a method that reduces and/or eliminates photoresist poisoning.
SUMMARY OF THE INVENTION
The instant invention describes a method to reduce photoresist poisoning from silicon carbide layers. In particular the method comprises performing a deposition chamber pre-coat process comprising trimethylsilane and oxygen prior to silicon carbide layer formation. The silicon carbide layer is formed on a dielectric layer using a deposition process comprising trimethylsilane. Following the formation of the silicon carbide hardmask layer, a patterned photoresist layer is formed on the silicon carbide layer; and the silicon carbide layer is patterned using the patterned photoresist layer as a mask.


REFERENCES:
patent: 4847215 (1989-07-01), Hanaki et al.
patent: 6349669 (2002-02-01), Matsumura et al.
patent: 6365527 (2002-04-01), Yang et al.
patent: 6383907 (2002-05-01), Hasegawa et al.

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