Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2001-06-11
2002-12-31
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Reexamination Certificate
active
06500738
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming integrated circuitry and to semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry.
BACKGROUND OF THE INVENTION
Processing of semiconductor devices typically involves many steps which include masking, doping, and etching. Each time one of these steps is performed, certain risks can arise which can jeopardize the integrity of a wafer being processed. For example, a mask misalignment error can cause a subsequent etch to undesirably etch into wafer or substrate structure which can cause catastrophic failure. Accordingly, it is desirable to reduce the number of processing steps utilized in the formation of integrated circuitry.
This invention arose out of concerns associated with reducing the number of processing steps needed in the formation of integrated circuitry. This invention also arose out of concerns associated with improving the manner in which integrated circuitry memory devices, and in particular dynamic random access memory (DRAM) devices are fabricated.
SUMMARY OF THE INVENTION
Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive fine is removed through the other opening to at least partially form a contact opening over the other conductive line.
REFERENCES:
patent: 4232439 (1980-11-01), Shibata
patent: 4343657 (1982-08-01), Ito et al.
patent: 4734383 (1988-03-01), Ikeda et al.
patent: 5017506 (1991-05-01), Shen et al.
patent: 5459085 (1995-10-01), Pasen et al.
patent: 5637525 (1997-06-01), Dennison
patent: 5656520 (1997-08-01), Watanabe
patent: 5668065 (1997-09-01), Lin
patent: 5686324 (1997-11-01), Wang et al.
patent: 5731236 (1998-03-01), Chou et al.
patent: 5731242 (1998-03-01), Parat et al.
patent: 5766992 (1998-06-01), Chou et al.
patent: 5795809 (1998-08-01), Gardner et al.
patent: 5821140 (1998-10-01), Jost et al.
patent: 5856227 (1999-01-01), Yu et al.
patent: 5985711 (1999-11-01), Lim
patent: 6015730 (2000-01-01), Wang et al.
patent: 6025255 (2000-02-01), Chen et al.
patent: 6165880 (2000-12-01), Yaung et al.
patent: 6177339 (2001-01-01), Juengling
patent: 6337261 (2002-01-01), Juengling
Wolf, Ph.D. et al., Silicon Processing for the VLSI Era—vol. 1—Processing Technology ©1986, p. 283 only.
Christianson Keith
Micro)n Technology, Inc.
Wells St. John P.S.
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