Synchronous SRAM circuit

Details Synchronous SRAM circuit Synchronous SRAM circuit

1999-06-22

2002-11-19

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S218000, C711S203000, C711S168000, C365S189011

Reexamination Certificate

active

06484231

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and in particular to a synchronous SRAM circuit.
2. Background of the Related Art
FIG. 1
illustrates a related art synchronous SRAM circuit. As shown in
FIG. 1
, a cell array
6
includes a plurality of cells each storing a cell data. The plurality of the cells are grouped within a plurality of cell blocks
61
through
64
. The following description of the related art SRAM assumes the number of the cell blocks
61
through
64
and the number of column selection signals C/S:n are four (4), respectively.
An address register
1
latches an external address signal Add inputted from the outside in accordance with a clock signal CLK. In accordance with the clock signal CLK, a control register
2
latches various control signals Cout such as read and write signals, and control signals /ADSP, /ADSC, /ADV, which are used for determining the burst mode. A control unit
3
receives control signals /ADSP and /ADSC from the control register
2
and controls corresponding elements.
A counter
4
counts a column selection signal C/S:n inputted from the address register
1
in accordance with a burst mode signal BMS to generate an internal address signal. An address decoder
5
selects one cell among the cells of the cell array
6
and allows a corresponding cell data to be outputted from the selected cell in accordance with the external address signal Add or the internal address signal.
A sense amplifier
7
is formed of a plurality of sense amplifiers
71
through
74
. Each of the sense amplifiers
71
-
74
is connected with a corresponding one of the cell blocks
61
through
64
and receives a cell data for amplification from the corresponding one of the cell blocks
61
through
64
. An output register
8
latches a cell data latched by the sense amplifier
7
and outputs the stored cell data to an input and output pad
9
under control of the control unit
3
. The data is output to the outside from the input and output pad
9
.
In addition, an internal register (not shown) is further provided for inputting a new cell data to the sense amplifier
7
(i.e., a writing operation) under control of the control unit
3
. The description of the internal register is omitted.
A cell data reading operation of the related art synchronous SRAM will now be described. An external address signal Add inputted to the address register
1
is latched in accordance with a clock signal CLK and is inputted into the counter
4
and the address decoder
5
, respectively. The control signals /ADSP, /ADSC, /ADV inputted into the control register
2
are latched by the control register
2
in accordance with the clock signal CLK.
The control unit
3
determines the level of a control signal CS, which is based on the logic states of the control signals /ADSP, /ADSC, /ADV. The control unit
3
combines the control signals /ADSP and /ADSC to generate a burst mode signal BMS. The counter
4
is enabled by the burst signal BMS and counts the column selection signal C/S:n inputted from the address register
1
. As a result, the counter
4
outputs the internal address signal to the address decoder
5
.
The address decoder
5
decodes the external address signal or the internal address signal and outputs the decoded signal to the cell array
6
. In addition, the address decoder
5
outputs cell block coding signals ANI_I and ANO_I. One block is selected from a plurality of cell blocks
61
through
64
. If the counter
4
does not generate the internal address, the address decoder
5
decodes the external address signal Add.
One cell in the cell block is selected in accordance with a decoding signal from the address decoder
5
. The cell data stored in the selected cell is amplified by the sense amplifier
7
and is latched by the output register
8
. The latched cell data is outputted from the output register
8
to the outside through the input and output pad
9
in accordance with a control signal from the control unit
3
.
The method of the related art SRAM for selecting a plurality of cells is determined based on whether the address inputted into the address decoder
5
is the external address or the internal address. When the address decoder
5
operates in accordance with the external address signal Add, the operation of the entire circuit is performed in synchronization with an external clock signal CLK. This is called single read mode. When the address decoder
5
operates in accordance with an internal address signal from the counter
4
, the operation of the entire circuit is performed irrespective of the external clock signal. This is called burst read mode.
The single and burst read modes will now be described with reference to
FIG. 2
assuming that a number of clock pulses used for implementing a read operation of the related art SRAM is two (2). Namely, it is assumed that the latency is 2. In addition, the description assumes that one data is formed of four cell data, and each cell data is formed of a word unit.
FIG. 2
is a wave form diagram illustrating timing of each element of the related art synchronous SRAM circuit.
FIG. 2
illustrates the clock signal CLK, the control signals /ADSP, /ADSC, /ADV, the address signal Add, and data DATA Out. The two control signals /ADSP and /ADSC are used for setting the burst read mode. If both the control signals /ADSP and /ADSC are low level, the entire circuit operates in the burst read mode. According to the timing of
FIG. 2
, at a time tl where a first clock signal is generated, the mode is the single read mode, and at the time after the time t
1
, the mode is the burst read mode.
At the time t
1
shown in
FIG. 2
, when the first clock signal is generated, the external address A
o
is latched, and the cell data stored in a predetermined cell is read in accordance with the external address A
o
. The read cell data Q
1
(A
o
) is latched into the output register
8
through the sense amplifier
7
.
At the time t
2
, if the second clock signal is generated, the cell data Q
1
(A
o
) stored in the output register
8
is outputted to the outside, and the external address signal A
1
is latched. At the time t
2
, the first cell data Q
1
(A
o
) is outputted to the outside, and the second cell data Q
1
(A
1
) is latched to the output register
8
. Therefore, as described hereinabove, two clock pulses are used until the cell data Q
1
(A
o
) is outputted after an external address is inputted.
At the time t
2
, the cell data Q
1
(A
o
) stored in the output register
8
is outputted, and at the same time the control signal /ADSC is shifted to a low level. At this time, since the control signal /ADSP is also a low level, the entire circuit begins to operate in the burst read mode. Namely, it is determined whether the mode is the burst read mode at every time tl, t
2
, t
3
, . . . at which each clock pulse is generated.
If the control signal /ADV is a low level in the burst read mode, the counter
4
increases the internal address. Namely, the counter
4
counts the column selection signal CS:n. The counted value is inputted into the address decoder
5
, and the address decoder
5
outputs a decoded signal for the first cell block
61
of the cell array
6
, and the cell data in the interior of the coded cell block
61
is read. The cell data read from the cell block
61
is latched to the output register
8
through the first sense amplifier
71
.
If the internal address is increased by the counter
4
, the second block
62
of the cell array
6
is coded, and the cell data in the interior of the coded block
62
is read. The cell data read from the cell block
62
is latched to the output register
8
through the second sense amplifier
72
. The above-described operation is repeated until the four cell data forming the corresponding data are outputted. Thus, the four cell data Q
1
(A
1
), Q
2
(A
1
), Q
3
(A
1
), Q
4
(A
1
) form one data.
The four cell data Q
1
(A
1
), Q
2
(A
1
), Q
3
(A
1
), Q
4
(A
1
) are sequentially outputted. To output the four cell data, five

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