Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-10
2002-11-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S533000, C438S591000, C438S595000, C438S660000, C438S776000, C438S786000
Reexamination Certificate
active
06486062
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor fabrication, and in particular to self-aligned silicide (salicide) technology utilizing nickel silicide (NiSi).
BACKGROUND ART
Salicide technology is improving the performance characteristics of semiconductor devices, and is becoming an essential component of semiconductor device fabrication. As gate electrode lengths are scaled down, the source/drain junctions and polycrystalline line width must also be scaled down. However, scaling down the source/drain junctions and polycrystalline line width increases parasitic resistance in the source/drain diffusion layers and gate electrode diffusion layer, and also increases the sheet and contact resistance of the gate electrode and source/drain regions. Salicide technology reduces parasitic, sheet, and contact resistance in the source/drain diffusion layers and gate electrode diffusion layer that results from scaling down the source/drain junctions and polycrystalline line width. Salicide technology comprises forming silicide layers on the source/drain regions and/or on the gate electrode in a self-aligned manner.
Silicides are typically formed by reacting a metal with crystallized silicon (Si) within a specified temperature range for a specific period of time. Silicide layers may be self-aligned by different techniques. For example, selectively depositing the metal on the top of the gate electrode and on the source/drain regions of a semiconductor device prior to an annealing process causes only the Si of the source/drain regions and the top of the gate electrode to form silicide upon annealing. Alternatively, sidewall spacers on the sides of the gate electrode constructed of a material that does not react with the metal layer allow a blanket layer of metal to be deposited over a semiconductor device while restricting silicide formation to the exposed source/drain regions and the top of the gate electrode during an annealing process. During the annealing process, the semiconductor device is heated to a reaction temperature, and held at the reaction temperature for a period of time, causing the metal layer to react with the crystallized Si that the metal contacts, thus forming a silicide layer interfacing with the remaining crystallized Si substrate of the source/drain regions and/or the gate electrode. Multiple annealing steps may be employed. Various metals react with Si to form a silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create silicides when manufacturing semiconductor devices utilizing salicide technology.
Use of a TiSi
2
layer imposes limitations on the manufacture of semiconductor devices. A significant limitation is that the sheet resistance for lines narrower than 0.35 micrometers is high, i.e., as TiSi
2
is formed in a narrower and narrower line, the resistance increases. Another significant limitation is that TiSi
2
initially forms a high resistivity phase (C49), and transformation from C49 to a low resistivity phase (C54) is nucleation limited, i.e., a high temperature is required to affect the phase change.
Cobalt silicide, unlike TiSi
2
, exhibits less linewidth dependence of sheet resistance. However, CoSi
2
consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with Si on insulator (SIO) substrates. Without enough Si to react with Co to form CoSi
2
, a thin layer of CoSi
2
results. The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material, thus a thicker silicide layer increases semiconductor device speed, while a thin silicide layer reduces device speed.
Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi
2
and CoSi
2
because many limitations associated with TiSi
2
and CoSi
2
are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni, and Co, through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the sink/drain regions. The reaction that forms NiSi requires less Si than when TiSi
2
and CoSi
2
are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silicide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi
2
and CoSi
2
. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
Although the use of NiSi in salicide technology has certain advantages over utilizing TiSi
2
and CoSi
2
, there are problems using NiSi in certain situations. Forming NiSi on doped, crystallized Si usually produces a smooth interface between the NiSi layer and the doped, crystallized Si layer. However, when crystallized Si is doped with arsenic (As), a rough interface between the NiSi and the doped, crystallized Si forms, which leads to certain problems.
Salicide technology employing NiSi has proven problematic because of interface roughness. A rough interface increases junction leakage, creates the possibility of spiking, and limits the thickness to which the silicide layer can be grown. Spiking occurs when the silicide layer interface is rough enough for spikes to form in the interface between the silicide layer and the crystallized Si comprising the source/drain region. For example,
FIG. 1
depicts a prior art silicide layer
130
formed on semiconductor device
150
. The interface
112
between the silicide
130
and the source/drain region
115
is rough and contains spikes
120
. If a spike
120
is large enough to reach the bottom
125
of the source/drain region
115
increased junction leakage will occur.
FIGS. 2 and 3
depict a prior art method of forming a semiconductor device
150
with a NiSi layer
205
over an As doped source/drain
115
. In
FIG. 2
, a Si substrate
102
has a gate dielectric layer
110
formed on it. A poly-silicon gate
100
is provided on a gate dielectric layer
110
. Sidewalls
105
are formed on the sides of the poly-silicon gate
100
and are comprised of a material that does not react with Ni. The Si substrate
102
is doped with As, i.e., by implantation. Arsenic ions are implanted into the Si substrate
102
, as well as into the poly-silicon gate
100
to form, source/drain regions
115
. An annealing process recrystallizes the substrate
102
, which is often amorphized during the As ion implantation. The annealing process also activates the As that has been implanted as a dopant. A layer of Ni
120
is then deposited over the semiconductor device
150
. Heat is again applied to the semiconductor device during a second annealing process in order to react the layer of Ni
120
with the Si substrate
102
and with the poly-silicon gate
100
. Un-reacted Ni is removed by a selective etching process, for example.
FIG. 3
depicts the prior art semiconductor device
150
after the second annealing process, and the un-reacted metal has been removed. Because of the reaction between the As ions in the substrate
102
and the Ni atoms diffused from the Ni layer
120
, a rough interface
200
is formed between the NiSi layer
205
and the As doped source/drain regions
115
.
Several problems, as noted previously, are associated with a rough interface between the NiSi layer and the Si substrate. A rough interface increases junction leakage, and creates the possibility of spike formation. A rough interface also limits the thickness to which a silicide layer can be grown, thus limiting how low the resistivity of the silicide layer is.
There exists a need for salicide technology that enables a reduction in the parasitic sheet re
Buynoski Matthew S.
Kluth George J.
Advanced Micro Devices , Inc.
Berry Renee R
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